Fix spelling errors

3 files changed, 6 insertions, 6 deletions

diff --git a/src/q.tex b/src/q.tex
index 835fe08..e581920 100644
--- a/src/q.tex
+++ b/src/q.tex
@@ -238,7 +238,7 @@ quad-precision bit patterns must be moved to the integer registers via
 memory.
 
 \begin{commentary}
-RV128 will spuport FMV.X.Q and FMV.Q.X in the Q extension.
+RV128 will support FMV.X.Q and FMV.Q.X in the Q extension.
 \end{commentary}
 
 \section{Quad-Precision Floating-Point Compare Instructions}
diff --git a/src/rv128.tex b/src/rv128.tex
index ef78dd9..64515e3 100644
--- a/src/rv128.tex
+++ b/src/rv128.tex
@@ -48,7 +48,7 @@ added.  The ``*D'' instructions consume two major opcodes (OP-IMM-64
 and OP-64) in the standard 32-bit encoding.
 
 \begin{commentary}
-  To improve compatibilty with RV64, in a reverse of how RV32 to RV64
+  To improve compatibility with RV64, in a reverse of how RV32 to RV64
   was handled, we might change the decoding around to rename RV64I ADD
   as a 64-bit ADDD, and add a 128-bit ADDQ in what was previously the
   OP-64 major opcode (now renamed the OP-128 major opcode).
diff --git a/src/v.tex b/src/v.tex
index e5a17be..271a4c9 100644
--- a/src/v.tex
+++ b/src/v.tex
@@ -588,7 +588,7 @@ unit state.
   and to provide additional security when context swapping.  Zero is
   also a convenient initial value for some loops.
 
-  In-order implementations will probaby use a flag bit per register to
+  In-order implementations will probably use a flag bit per register to
   mux in 0 instead of garbage values on each source until it is
   overwritten.  For in-order machines, vector lengths less than MVL
   complicate this zeroing, but these cases can be handled by adding a
@@ -624,7 +624,7 @@ instruction exception.
   extensions.  For example (and not limited to), new scalar types in
   new number systems, a complex type with real and imaginary
   components, a key-value type, or an application-specific structure
-  type with multiple consitituent fields.  Auxiliary type
+  type with multiple constituent fields.  Auxiliary type
   configuration state might be required in these cases.
 \end{commentary}
 
@@ -1123,7 +1123,7 @@ elements in the range [{\tt vl}:MAXVL-1] in the destination vector
 data register or destination vector predicate register to zero.
 
 \begin{commentary}
-  Requring zeroing of elements past the current active vector length
+  Requiring zeroing of elements past the current active vector length
   simplifies the design of units with renamed vector data registers.
   If the specification left destination elements unchanged, renaming
   implementations would have to copy the tail of the old destination
@@ -1308,7 +1308,7 @@ locations in decreasing memory order.
 \end{discussion}
 
 Vector loads/stores have a simple memory model, where each vector
-load/store is observed to complete sequentially in program order ony
+load/store is observed to complete sequentially in program order only
 the local hart, i.e., a vector load on a hart will observe all earlier
 vector stores on the same hart, and no later vector stores.