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| author | Andrew Waterman <andrew@sifive.com> | 2018-08-12 17:45:47 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-08-12 17:45:47 -0700 |
| commit | c643f44e6ec8026530ce808f4d26851f4badfda3 (patch) | |
| tree | 7cecde8688658f6d7719c666b2c797e3188d1201 | |
| parent | 6fad4fb56922bb3d27a2862e3adc9fcd3106d8ec (diff) | |
| download | riscv-isa-manual-c643f44e6ec8026530ce808f4d26851f4badfda3.zip riscv-isa-manual-c643f44e6ec8026530ce808f4d26851f4badfda3.tar.gz riscv-isa-manual-c643f44e6ec8026530ce808f4d26851f4badfda3.tar.bz2 | |
Minor tweaks
| -rw-r--r-- | src/intro.tex | 4 | ||||
| -rw-r--r-- | src/rv32.tex | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/intro.tex b/src/intro.tex index e17722a..59f7087 100644 --- a/src/intro.tex +++ b/src/intro.tex @@ -613,8 +613,8 @@ The following table shows the characteristics of each kind of trap: Handled by environment? & N & Y & Y & Y \\ \hline \end{tabular} - \caption{Characteristics of traps. Notes 1), termination may be - requested, 2) imprecise fatal traps might be observable by software.} + \caption{Characteristics of traps. Notes: 1) termination may be + requested; 2) imprecise fatal traps might be observable by software.} \end{table} The EEI defines for each trap whether it is handled precisely, though diff --git a/src/rv32.tex b/src/rv32.tex index 684fa03..9099a30 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -127,7 +127,7 @@ In the base RV32I ISA, there are four core instruction formats fixed 32 bits in length and must be aligned on a four-byte boundary in memory. An instruction-address-misaligned exception is generated on a taken branch or unconditional jump if the target address is not -four-byte aligned. This exception is report on the branch or jump +four-byte aligned. This exception is reported on the branch or jump instruction, not on the target instruction. No instruction-address-misaligned exception is generated for a conditional branch that is not taken. @@ -655,7 +655,7 @@ optimized away in decode). In particular, the instruction only reads one register. Also, an ADDI functional unit is more likely to be available in a superscalar design as adds are the most common operation. In particular, address-generation functional units can -execute ADDI using same hardware needed for base+offset address +execute ADDI using the same hardware needed for base+offset address calculations, while register-register ADD or logical/shift operations require additional hardware. \end{commentary} |