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| author | Andrew Waterman <andrew@sifive.com> | 2018-08-25 05:24:46 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-08-25 05:24:46 -0700 |
| commit | c011be7529fd98b9a31c72e7abc8566e02a71912 (patch) | |
| tree | 01b20d8d6bd79ef2af93605d074993f8c89f154e | |
| parent | 48df4e3688823c01dbca5e61b2f2e8cfb6ebd6d9 (diff) | |
| download | riscv-isa-manual-c011be7529fd98b9a31c72e7abc8566e02a71912.zip riscv-isa-manual-c011be7529fd98b9a31c72e7abc8566e02a71912.tar.gz riscv-isa-manual-c011be7529fd98b9a31c72e7abc8566e02a71912.tar.bz2 | |
Add semihosting note
| -rw-r--r-- | src/rv32.tex | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/rv32.tex b/src/rv32.tex index 9099a30..60723b6 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -1340,6 +1340,10 @@ supervisor-level operating system or debugger. ebreak # Break to debugger srai x0, x0, 7 # NOP encoding the semihosting call number 7 \end{verbatim} + Note that these three instructions must be 32-bit-wide instructions, + i.e., they mustn't be among the compressed 16-bit instructions + described in Chapter~\ref{compressed}. + The shift NOP instructions are still considered available for use as HINTS. |