Tweaks to M extension chapter

1 files changed, 8 insertions, 8 deletions

diff --git a/src/m.tex b/src/m.tex
index ca46f9c..66c11f8 100644
--- a/src/m.tex
+++ b/src/m.tex
@@ -58,12 +58,12 @@ most-significant word of the multiplier (which contains the sign bit)
 with the less-significant words of the multiplicand (which are unsigned).
 \end{commentary}
 
-MULW is an RV64I instruction, and multiplies the lower
-32 bits of the source registers, placing the sign-extension of the
-lower 32 bits of the result into the destination register.  MUL can be
-used to obtain the upper 32 bits of the 64-bit product, but signed
-arguments must be proper 32-bit signed values, whereas unsigned
-arguments must have their upper 32 bits clear.
+MULW is an RV64 instruction that multiplies the lower 32 bits of the source
+registers, placing the sign-extension of the lower 32 bits of the result
+into the destination register.  In RV64, MUL can be used to obtain the upper
+32 bits of the 64-bit product, but signed arguments must be proper 32-bit
+signed values, whereas unsigned arguments must have their upper 32 bits
+clear.
 
 \section{Division Operations}
 
@@ -101,11 +101,11 @@ cannot be the same as {\em rs1} or {\em rs2}).  Microarchitectures can
 then fuse these into a single divide operation instead of performing
 two separate divides.
 
-DIVW and DIVUW instructions are RV64I instructions, and divide the
+DIVW and DIVUW are RV64 instructions that divide the
 lower 32 bits of {\em rs1} by the lower 32 bits of {\em rs2}, treating
 them as signed and unsigned integers respectively, placing the 32-bit
 quotient in {\em rd}, sign-extended to 64 bits.  REMW and REMUW
-instructions are only valid for RV64, and provide the corresponding
+are RV64 instructions that provide the corresponding
 signed and unsigned remainder operations respectively. Both REMW and
 REMUW always sign-extend the 32-bit result to 64 bits, including on a
 divide by zero.