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authorKrste Asanovic <krste@eecs.berkeley.edu>2018-08-06 18:15:32 -0700
committerKrste Asanovic <krste@eecs.berkeley.edu>2018-08-06 18:15:32 -0700
commitaba09b1c9225ddf4f388a42fb87b898e6624d4c9 (patch)
tree4a4c4035d646d05a33922343c3a38aea37d7c5e1
parentb285e77d9334a29fac058c0cf43ce4037c9080aa (diff)
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Removed statement that *W instructions are RV64 only.
-rw-r--r--src/m.tex4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/m.tex b/src/m.tex
index 16ab6d9..ca46f9c 100644
--- a/src/m.tex
+++ b/src/m.tex
@@ -58,7 +58,7 @@ most-significant word of the multiplier (which contains the sign bit)
with the less-significant words of the multiplicand (which are unsigned).
\end{commentary}
-MULW is only valid for RV64, and multiplies the lower
+MULW is an RV64I instruction, and multiplies the lower
32 bits of the source registers, placing the sign-extension of the
lower 32 bits of the result into the destination register. MUL can be
used to obtain the upper 32 bits of the 64-bit product, but signed
@@ -101,7 +101,7 @@ cannot be the same as {\em rs1} or {\em rs2}). Microarchitectures can
then fuse these into a single divide operation instead of performing
two separate divides.
-DIVW and DIVUW instructions are only valid for RV64, and divide the
+DIVW and DIVUW instructions are RV64I instructions, and divide the
lower 32 bits of {\em rs1} by the lower 32 bits of {\em rs2}, treating
them as signed and unsigned integers respectively, placing the 32-bit
quotient in {\em rd}, sign-extended to 64 bits. REMW and REMUW