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| author | Andrew Waterman <andrew@sifive.com> | 2018-09-23 20:24:25 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-09-23 20:25:40 -0700 |
| commit | 86802858af4f070046fa4c6b530dbaa04c1da254 (patch) | |
| tree | 067642cc3e1f39e2207e40cff96f17f42b5cdc22 | |
| parent | 693ad48fc347bb613b95f6ebafc2e062428c5bd5 (diff) | |
| download | riscv-isa-manual-86802858af4f070046fa4c6b530dbaa04c1da254.zip riscv-isa-manual-86802858af4f070046fa4c6b530dbaa04c1da254.tar.gz riscv-isa-manual-86802858af4f070046fa4c6b530dbaa04c1da254.tar.bz2 | |
unused misa fields are wlrl, not wiri
| -rw-r--r-- | src/machine.tex | 2 | ||||
| -rw-r--r-- | src/priv-preface.tex | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index 7bebe67..3012627 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -35,7 +35,7 @@ mechanism. \instbitrange{25}{0} \\ \hline \multicolumn{1}{|c|}{MXL[1:0] (\warl)} & -\multicolumn{1}{c|}{\wiri} & +\multicolumn{1}{c|}{\wlrl} & \multicolumn{1}{c|}{Extensions[25:0] (\warl)} \\ \hline 2 & MXLEN-28 & 26 \\ diff --git a/src/priv-preface.tex b/src/priv-preface.tex index c4c4824..79a2844 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -14,6 +14,7 @@ architecture proposal. Changes from version 1.10 include: \item The virtual-memory system no longer permits supervisor mode to execute instructions from user pages, regardless of the SUM setting. \item Made the {\tt mstatus}.MPP field \warl, rather than \wlrl. +\item Made the unused {\tt misa} fields \wlrl, rather than \wiri. \item Required all harts in a system to employ the same PTE-update scheme as each other. \item Rectified an editing error that misdescribed the mechanism by which {\tt mstatus}.{\em x}IE is written upon an exception. |