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| author | Andrew Waterman <aswaterman@gmail.com> | 2018-10-04 15:06:29 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-04 15:06:29 -0700 |
| commit | 71597dd3ad89a2262d240680793586a8ebdec308 (patch) | |
| tree | 3109940a0dbc70f560338fb6caab15d512395f1e | |
| parent | 4abbead1038fa9366b177d289ebcf0b8da503617 (diff) | |
| download | riscv-isa-manual-71597dd3ad89a2262d240680793586a8ebdec308.zip riscv-isa-manual-71597dd3ad89a2262d240680793586a8ebdec308.tar.gz riscv-isa-manual-71597dd3ad89a2262d240680793586a8ebdec308.tar.bz2 | |
Add marchid management document (#234)
* Fix broken link
* Add marchid document
| -rw-r--r-- | README.md | 3 | ||||
| -rw-r--r-- | marchid.md | 21 | ||||
| -rw-r--r-- | src/rv32.tex | 2 |
3 files changed, 25 insertions, 1 deletions
@@ -17,3 +17,6 @@ https://riscv.org/specifications/ Compiled versions of the most recent drafts of the specifications are available at https://github.com/riscv/riscv-isa-manual/releases/latest + +The canonical list of open-source RISC-V implementations' marchid CSR values +is available at https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md diff --git a/marchid.md b/marchid.md new file mode 100644 index 0000000..6dd41aa --- /dev/null +++ b/marchid.md @@ -0,0 +1,21 @@ +Open-Source RISC-V Architecture IDs +======================================== + +Every RISC-V hart provides an marchid CSR that encodes its base +microarchitecture. Any hart may report an architecture ID of 0, indicating +unspecified origin. Commercial implementations (those with nonzero mvendorid) +may encode any value in marchid with the most-significant bit set, with the +low-order bits formatted in a vendor-specific manner. Open-source +implementations (which may or may not have a nonzero mvendorid) have the +most-significant bit clear, with a globally unique pattern in the low-order +bits. + +This document contains the canonical list of open-source RISC-V implementations +and their architecture IDs. Open-source project maintainers may make pull +requests against this repository to request the allocation of an architecture +ID. + +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Project Name | Maintainers | Point of Contact | Architecture ID | Project URL +-------------|-------------------------------|---------------------------------------------------------|-----------------|--------------------------------------------------- +Rocket | SiFive, UC Berkeley | [Andrew Waterman](mailto:andrew@sifive.com), SiFive | 1 | https://github.com/freechipsproject/rocket-chip diff --git a/src/rv32.tex b/src/rv32.tex index 60723b6..0aab4f5 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -202,7 +202,7 @@ U-type \\ The RISC-V ISA keeps the source ({\em rs1} and {\em rs2}) and destination ({\em rd}) registers at the same position in all formats to simplify decoding. Except for the 5-bit immediates used in CSR -instructions (Section~\ref{sec:csrinsts}), immediates are always +instructions (Chapter~\ref{csrinsts}), immediates are always sign-extended, and are generally packed towards the leftmost available bits in the instruction and have been allocated to reduce hardware complexity. In particular, the sign bit for all immediates is always |