Added more commentary on illegal instruction encodings.

1 files changed, 28 insertions, 11 deletions

diff --git a/src/intro.tex b/src/intro.tex
index 5979c99..22a57c3 100644
--- a/src/intro.tex
+++ b/src/intro.tex
@@ -277,12 +277,12 @@ extensions and are made available for vendor-specific non-standard
 extensions.  We use the term {\em non-conforming} to describe a
 non-standard extension that uses either a standard or a reserved
 encoding (i.e., custom extensions are {\em not} non-conforming).
-Instruction-set extensions may provide slightly different
-functionality depending on the width of the base integer instruction
-set.  Chapter~\ref{extensions} describes various ways of extending the
-RISC-V ISA.  We have also developed a naming convention for RISC-V
-base instructions and instruction-set extensions, described in detail
-in Chapter~\ref{naming}.
+Instruction-set extensions are generally shared but may provide slightly different
+functionality depending on the base ISA.  Chapter~\ref{extensions}
+describes various ways of extending the RISC-V ISA.  We have also
+developed a naming convention for RISC-V base instructions and
+instruction-set extensions, described in detail in
+Chapter~\ref{naming}.
 
 To support more general software development, a set of standard
 extensions are defined to provide integer multiply/divide, atomic
@@ -358,11 +358,6 @@ addition to the first 5$\times$16-bit words.  The encoding with bits
 [14:12] set to {\tt 111} is reserved for future longer instruction
 encodings.
 
-The encodings with bits [15:0] all zeros are illegal.  These instructions are
-considered to be of minimal length: 16 bits if any 16-bit instruction-set
-extension is present, otherwise 32 bits.  The encoding with bits [ILEN-1:0]
-all ones is also illegal; this instruction is considered to be ILEN bits long.
-
 \begin{figure}[hbt]
 {
 \begin{center}
@@ -444,6 +439,13 @@ instruction-set extensions.  Further, if the implementation also does
 not need instructions $>$32-bits in length, it can recover a further
 four major opcodes.
 \end{samepage-commentary}
+
+Encodings with bits [15:0] all zeros are defined as illegal
+instructions.  These instructions are considered to be of minimal
+length: 16 bits if any 16-bit instruction-set extension is present,
+otherwise 32 bits.  The encoding with bits [ILEN-1:0] all ones is also
+illegal; this instruction is considered to be ILEN bits long.
+
 \begin{commentary}
 We consider it a feature that any length of instruction containing all
 zero bits is not legal, as this quickly traps erroneous jumps into
@@ -451,6 +453,21 @@ zeroed memory regions. Similarly, we also reserve the instruction
 encoding containing all ones to be an illegal instruction, to catch
 the other common pattern observed with unprogrammed non-volatile
 memory devices, disconnected memory buses, or broken memory devices.
+
+Software can rely on a naturally aligned 32-bit word containing zero
+to act as an illegal instruction on all RISC-V implementations, to be
+used by software where an illegal instruction is explicitly desired.
+Defining a corresponding known illegal value for all ones is more
+difficult due to the variable-length encoding.  Software cannot
+generally use the illegal value of ILEN bits of all 1s, as software
+might not know ILEN for the eventual target machine (e.g., if software
+is compiled into a standard binary library used by many different
+machines).  Defining a 32-bit word of all ones as illegal was also
+considered, as all machines must support a 32-bit instruction size,
+but this requires the instruction-fetch unit on machines with
+ILEN$>$32 report an illegal instruction exception rather than access
+fault when such an instruction borders a protection boundary,
+complicating variable-instruction-length fetch and decode.
 \end{commentary}
 
 The base RISC-V ISA has a little-endian memory system, but