diff options
author | Andrew Waterman <andrew@sifive.com> | 2018-08-29 13:39:48 -0700 |
---|---|---|
committer | Andrew Waterman <andrew@sifive.com> | 2018-08-29 13:47:24 -0700 |
commit | 3c8d95243aea56c97161412f3f0a2fa24139cadf (patch) | |
tree | 25ea55d1d06138c7c6ba7500065c73a245aad143 | |
parent | eb7817141bbbaa94157d65ef10c33a280dba1434 (diff) | |
download | riscv-isa-manual-3c8d95243aea56c97161412f3f0a2fa24139cadf.zip riscv-isa-manual-3c8d95243aea56c97161412f3f0a2fa24139cadf.tar.gz riscv-isa-manual-3c8d95243aea56c97161412f3f0a2fa24139cadf.tar.bz2 |
Clarify that mtval/mepc are set on interrupts, too
-rw-r--r-- | src/machine.tex | 8 | ||||
-rw-r--r-- | src/riscv-privileged.tex | 2 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/machine.tex b/src/machine.tex index 024daca..9189a81 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1729,8 +1729,8 @@ addresses. Implementations may convert some invalid address patterns into other invalid addresses prior to writing them to {\tt mepc}. When a trap is taken into M-mode, {\tt mepc} is written with the virtual -address of the instruction that encountered the exception. Otherwise, -{\tt mepc} is never written by the implementation, though it may be +address of the instruction that encountered the exception or was interrupted. +Otherwise, {\tt mepc} is never written by the implementation, though it may be explicitly written by software. \begin{figure}[h!] @@ -1860,9 +1860,9 @@ When a hardware breakpoint is triggered, or an instruction-fetch, load, or store address-misaligned, access, or page-fault exception occurs, {\tt mtval} is written with the faulting virtual address. On an illegal instruction trap, {\tt mtval} may be written with the first XLEN or ILEN -bits of the faulting instruction as described below. For other exceptions, +bits of the faulting instruction as described below. For other traps, {\tt mtval} is set to zero, but a future standard may redefine {\tt - mtval}'s setting for other exceptions. + mtval}'s setting for other traps. \begin{commentary} The {\tt mtval} register replaces the {\tt mbadaddr} register in diff --git a/src/riscv-privileged.tex b/src/riscv-privileged.tex index d890dd6..85c5af0 100644 --- a/src/riscv-privileged.tex +++ b/src/riscv-privileged.tex @@ -39,7 +39,7 @@ Christopher Celio, Chuanhua Chang, David Chisnall, Anthony Coulter, Palmer Dabbe Dalrymple, Dennis Ferguson, Mike Frysinger, John Hauser, David Horner, Olof Johansson, Yunsup Lee, Andrew Lutomirski, Jonathan Neusch{\"a}fer, Rishiyur Nikhil, Stefan O'Rear, Albert Ou, John Ousterhout, David Patterson, Dmitri -Pavlov, Colin Schmidt, Wesley Terpstra, Matt Thomas, Tommy Thorn, Ray +Pavlov, Kade Phillips, Colin Schmidt, Wesley Terpstra, Matt Thomas, Tommy Thorn, Ray VanDeWalker, Megan Wachs, Steve Wallach, Andrew Waterman, Clifford Wolf, and Reinoud Zandijk. |