Removed text that implied there was a maximum alignment requirement

for mtvec, and clarified that different modes can have different
mtvec alignment constraints.

4 files changed, 18 insertions, 9 deletions

diff --git a/src/l.tex b/src/l.tex
index dcc6c75..30c688d 100644
--- a/src/l.tex
+++ b/src/l.tex
@@ -1,5 +1,8 @@
 \chapter{``L'' Standard Extension for Decimal Floating-Point, Version 0.0}
 
+{\bf This chapter is a draft proposal that has not been ratified by
+  the Foundation.}
+
 This chapter is a placeholder for the specification of a standard
 extension named ``L'' designed to support decimal floating-point
 arithmetic as defined in the IEEE 754-2008 standard.
diff --git a/src/machine.tex b/src/machine.tex
index 8ca2059..8ec2e61 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -1034,8 +1034,6 @@ field, whereas interrupts cause the {\tt pc} to be set to the address in
 the BASE field plus four times the interrupt cause number.  For example,
 a machine-mode timer interrupt (see Table~\ref{mcauses}) causes the {\tt pc}
 to be set to BASE+{\tt 0x1c}.
-Setting MODE=Vectored may impose an additional alignment constraint on BASE,
-requiring $1\times$, $2\times$, or $4\times$MXLEN-byte alignment.
 
 \begin{commentary}
 When vectored interrupts are enabled, interrupt cause 0, which corresponds to
@@ -1045,6 +1043,15 @@ user-mode software interrupts are either disabled or delegated to
 a less-privileged mode.
 \end{commentary}
 
+An implementation may have different alignment constraints for
+different modes.  In particular, MODE=Vectored may have stricter
+alignment constraints than MODE=Direct.
+
+\begin{commentary}
+  Allowing coarser alignments in Vectored mode enables vectoring to be
+  implemented without a hardware adder circuit.
+\end{commentary}
+
 \begin{commentary}
 Reset and NMI vector locations are given in a platform specification.
 \end{commentary}
diff --git a/src/preamble.tex b/src/preamble.tex
index 277d409..cb66be4 100644
--- a/src/preamble.tex
+++ b/src/preamble.tex
@@ -71,6 +71,7 @@
   \vspace{-0.2in}
 }
 
+
 \newenvironment{samepage-commentary}
 {\begin{samepage} \begin{commentary}}
 {\end{commentary} \end{samepage}}
@@ -136,5 +137,3 @@
 \newcommand{\wlrl}{\textbf{WLRL}}
 \newcommand{\warl}{\textbf{WARL}}
 
-
-
diff --git a/src/rv32e.tex b/src/rv32e.tex
index 8d4b5ea..71ff45f 100644
--- a/src/rv32e.tex
+++ b/src/rv32e.tex
@@ -1,11 +1,11 @@
 \chapter{RV32E Base Integer Instruction Set, Version 1.9}
 \label{rv32e}
 
-This chapter describes the RV32E base integer instruction set, which
-is a reduced version of RV32I designed for embedded systems.  The only
-change is to reduce the number of integer registers to 16.  This
-chapter only outlines the differences between RV32E and RV32I, and so
-should be read after Chapter~\ref{rv32}.
+This chapter describes a draft proposal for the RV32E base integer
+instruction set, which is a reduced version of RV32I designed for
+embedded systems.  The only change is to reduce the number of integer
+registers to 16.  This chapter only outlines the differences between
+RV32E and RV32I, and so should be read after Chapter~\ref{rv32}.
 
 \begin{commentary}
 RV32E was designed to provide an even smaller base core for embedded