Merge branch 'master' of github.com:riscv/riscv-isa-manual

1 files changed, 5 insertions, 7 deletions

diff --git a/src/machine.tex b/src/machine.tex
index 0deda94..8d717af 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -1388,13 +1388,13 @@ Synchronous exceptions are of lower priority than all interrupts.
   The machine-level interrupt fixed-priority ordering rules were developed
   with the following rationale.
   
-  The platform-specific machine-level interrupt sources in bits 16 and
-  above have the highest service priority to support very fast local
-  vectored interrupts.
-  
   Interrupts for higher privilege modes must be serviced before
   interrupts for lower privilege modes to support pre-emption.
 
+  The platform-specific machine-level interrupt sources in bits 16 and above
+  have platform-specific priority, but are typically chosen to have the
+  highest service priority to support very fast local vectored interrupts.
+
   External interrupts are handled before internal (timer/software)
   interrupts as external interrupts are usually generated by devices
   that might require low interrupt service times.
@@ -2981,9 +2981,7 @@ that affects either the physical memory that holds the page tables or the
 physical memory to which the page tables point, M-mode software must
 synchronize the PMP settings with the virtual memory system.  This is
 accomplished by executing an SFENCE.VMA instruction with {\em rs1}={\tt x0}
-and {\em rs2}={\tt x0}, after the PMP CSRs are written.  Note, SFENCE.VMA is
-only guaranteed to synchronize the PMP settings with the virtual memory system
-when it is executed in M-mode.
+and {\em rs2}={\tt x0}, after the PMP CSRs are written.
 
 If page-based virtual memory is not implemented, or when it is disabled,
 memory accesses check the PMP settings synchronously, so no fence is needed.