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| author | Andrew Waterman <andrew@sifive.com> | 2018-10-11 12:52:06 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-10-11 12:52:39 -0700 |
| commit | 1038d2301aa6a6a911ad9969c76de00f6bae6e79 (patch) | |
| tree | bd59c8a126e8087eec5155b6c3dc189f4598e8e6 | |
| parent | f0baef16897be3d07e6d91e46ebdc8b28494dfb0 (diff) | |
| download | riscv-isa-manual-1038d2301aa6a6a911ad9969c76de00f6bae6e79.zip riscv-isa-manual-1038d2301aa6a6a911ad9969c76de00f6bae6e79.tar.gz riscv-isa-manual-1038d2301aa6a6a911ad9969c76de00f6bae6e79.tar.bz2 | |
Fix an ambiguity in PLIC spec
Resolves #239
| -rw-r--r-- | src/plic.tex | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/plic.tex b/src/plic.tex index ebc3cf1..f976e49 100644 --- a/src/plic.tex +++ b/src/plic.tex @@ -99,9 +99,10 @@ support delegating external interrupts to lower-privilege modes, then the lower-privilege hart contexts will not be interrupt targets. Interrupt notifications generated by the PLIC appear in the {\tt meip}/{\tt seip}/{\tt ueip} bits of the {\tt mip}/{\tt sip}/{\tt - uip} registers for M/S/U modes respectively. The notifications -only appear in lower-privilege {\em x}{\tt ip} registers if external -interrupts have been delegated to the lower-privilege modes. + uip} registers for M/S/U modes, respectively. For the notifications +to appear in lower-privilege {\em x}{\tt ip} registers, the corresponding +external interrupts must have been delegated in the higher-privilege +{\em y}{\tt ideleg} registers. Each processor core must define a policy on how simultaneous active interrupts are taken by multiple hart contexts on the core. For the |