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| author | Andrew Waterman <andrew@sifive.com> | 2018-09-10 11:04:06 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-09-10 11:05:26 -0700 |
| commit | 03a079586fcbcd37ae1728e716dfc3f9b633c996 (patch) | |
| tree | 545c798444ed1123a431f6aaa7be04bb3a7a6b02 | |
| parent | 1c15f337015588c4c2cca2992dc132ed375f01c8 (diff) | |
| download | riscv-isa-manual-03a079586fcbcd37ae1728e716dfc3f9b633c996.zip riscv-isa-manual-03a079586fcbcd37ae1728e716dfc3f9b633c996.tar.gz riscv-isa-manual-03a079586fcbcd37ae1728e716dfc3f9b633c996.tar.bz2 | |
Add ECALL from S-mode cause to SCAUSE table
This won't ever happen if medeleg[9] is hardwired to 0, but medeleg[9]
isn't required to be hardwired to 0.
| -rw-r--r-- | src/supervisor.tex | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index bd432a1..c7d2fe1 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -637,8 +637,9 @@ so is only guaranteed to hold supported exception codes. 0 & 5 & Load access fault \\ 0 & 6 & Store/AMO address misaligned \\ 0 & 7 & Store/AMO access fault \\ - 0 & 8 & Environment call \\ - 0 & 9--11 & {\em Reserved} \\ + 0 & 8 & Environment call from U-mode \\ + 0 & 9 & Environment call from S-mode \\ + 0 & 10--11 & {\em Reserved} \\ 0 & 12 & Instruction page fault \\ 0 & 13 & Load page fault \\ 0 & 14 & {\em Reserved} \\ |