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| author | Andrew Waterman <andrew@sifive.com> | 2019-03-07 12:15:10 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-03-07 12:15:10 -0800 |
| commit | 47ca7ce69c566b4c59923d87ce7c1875f4ff4b80 (patch) | |
| tree | 9926c6adaacabb2286dd2d9bafd17768f08608b4 | |
| parent | f424d107ef9c0c6ed1f305b030b0413a98ffab73 (diff) | |
| download | riscv-isa-manual-47ca7ce69c566b4c59923d87ce7c1875f4ff4b80.zip riscv-isa-manual-47ca7ce69c566b4c59923d87ce7c1875f4ff4b80.tar.gz riscv-isa-manual-47ca7ce69c566b4c59923d87ce7c1875f4ff4b80.tar.bz2 | |
Restate FENCE.TSO constraints from Table 2.1 in the text
| -rw-r--r-- | src/rv32.tex | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/rv32.tex b/src/rv32.tex index d5d99a6..7a676a4 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -1206,7 +1206,9 @@ The fence mode field {\em fm} defines the semantics of the FENCE. A FENCE with {\em fm}=0000 orders all memory operations in its predecessor set before all memory operations in its successor set. -The optional FENCE.TSO instruction with {\em fm}=1000 orders all load +The optional FENCE.TSO instruction is encoded as a FENCE instruction +with {\em fm}=1000, {\em predecessor}=RW, and {\em successor}=RW. +FENCE.TSO orders all load operations in its predecessor set before all memory operations in its successor set, and all store operations in its predecessor set before all store operations in its successor set. This leaves non-AMO store |