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author | Andrew Waterman <andrew@sifive.com> | 2023-04-30 16:51:48 -0700 |
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committer | GitHub <noreply@github.com> | 2023-04-30 16:51:48 -0700 |
commit | f0f67a25df2ccb49cb4f4506a469870c46caa14d (patch) | |
tree | e667076b6c85a948925f19709b02a8d44280b437 | |
parent | 8dfbe9ac076e1b468414a85e0030e2e22b1add10 (diff) | |
parent | be9714d89ed4f8683b97ec1a738d87dfc1c9393d (diff) | |
download | riscv-isa-manual-f0f67a25df2ccb49cb4f4506a469870c46caa14d.zip riscv-isa-manual-f0f67a25df2ccb49cb4f4506a469870c46caa14d.tar.gz riscv-isa-manual-f0f67a25df2ccb49cb4f4506a469870c46caa14d.tar.bz2 |
Merge pull request #1029 from riscv/wide-csrs
Clarify behavior of explicit accesses to CSRs wider than XLEN
-rw-r--r-- | src/hypervisor.adoc | 55 | ||||
-rw-r--r-- | src/images/bytefield/mseccfg.adoc | 6 | ||||
-rw-r--r-- | src/machine.adoc | 27 | ||||
-rw-r--r-- | src/priv-csrs.adoc | 30 | ||||
-rw-r--r-- | src/priv-preface.adoc | 1 |
5 files changed, 64 insertions, 55 deletions
diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc index 775d025..00ccd46 100644 --- a/src/hypervisor.adoc +++ b/src/hypervisor.adoc @@ -557,15 +557,15 @@ cause a supervisor-level (HS-level) guest external interrupt. The enable bits in `hgeie` do not affect the VS-level external interrupt signal selected from `hgeip` by `hstatus`.VGEIN. -==== Hypervisor Environment Configuration Registers (`henvcfg` and `henvcfgh`) +==== Hypervisor Environment Configuration Register (`henvcfg`) -The `henvcfg` CSR is an HSXLEN-bit read/write register, formatted for -HSXLEN=64 as shown in <<henvcfg>>, that controls +The `henvcfg` CSR is a 64-bit read/write register, formatted +as shown in <<henvcfg>>, that controls certain characteristics of the execution environment when virtualization mode V=1. [[henvcfg]] -.Hypervisor environment configuration register (`henvcfg`) for HSXLEN=64. +.Hypervisor environment configuration register (`henvcfg`). include::images/bytefield/henvcfg.edn[] If bit FIOM (Fence of I/O implies Memory) is set to one in `henvcfg`, @@ -611,11 +611,10 @@ The definitions of the CBCFE and CBIE fields will be furnished by the forthcoming Zicbom extension. Their allocations within `henvcfg` may change prior to the ratification of that extension. -When HSXLEN=32, `henvcfg` contains the same fields as bits 31:0 of -`henvcfg` when HSXLEN=64. Additionally, when HSXLEN=32, `henvcfgh` is a -32-bit read/write register that contains the same fields as bits 63:32 -of `henvcfg` when HSXLEN=64. Register `henvcfgh` does not exist when -HSXLEN=64. +When XLEN=32, `henvcfgh` is a +32-bit read/write register that aliases bits 63:32 +of `henvcfg`. Register `henvcfgh` does not exist when +XLEN=64. ==== Hypervisor Counter-Enable Register (`hcounteren`) @@ -639,9 +638,9 @@ readable unless the applicable bits are set in both `hcounteren` and read-only zero, indicating reads to the corresponding counter will cause an exception when V=1. Hence, they are effectively *WARL* fields. -==== Hypervisor Time Delta Registers (`htimedelta`, `htimedeltah`) +==== Hypervisor Time Delta Register (`htimedelta`) -The `htimedelta` CSR is a read/write register that contains the delta +The `htimedelta` CSR is a 64-bit read/write register that contains the delta between the value of the `time` CSR and the value returned in VS-mode or VU-mode. That is, reading the `time` CSR in VS or VU mode returns the sum of the contents of `htimedelta` and the actual value of `time`. @@ -652,14 +651,12 @@ Because overflow is ignored when summing `htimedelta` and `time`, large values of `htimedelta` may be used to represent negative time offsets. ==== -.Hypervisor time delta register, HSXLEN=64. +.Hypervisor time delta register. include::images/bytefield/htimedelta.edn[] -For HSXLEN=32 only, `htimedelta` holds the lower 32 bits of the delta, -and `htimedeltah` holds the upper 32 bits of the delta. - -.Hypervisor time delata registers, HSXLEN=32. -include::images/bytefield/htimedeltah.edn[] +When XLEN=32, `htimedeltah` is a 32-bit read/write register +that aliases bits 63:32 of `htimedelta`. +Register `htimedeltah` does not exist when XLEN=64. ==== Hypervisor Trap Value Register (`htval`) @@ -1823,28 +1820,18 @@ An instruction is _HS-qualified_ if it would be valid to execute in HS-mode (for some values of the instruction's register operands), assuming fields TSR and TVM of CSR `mstatus` are both zero. -Special rules apply for CSR instructions that access 32-bit high-half +A special rule applies for CSR instructions that access 32-bit high-half CSRs such as `cycleh` and `htimedeltah`. When V=1 and -XLEN>32, an attempt to access a high-half supervisor-level -CSR, high-half hypervisor CSR, high-half VS CSR, or high-half -unprivileged CSR always raises an illegal instruction exception. And in -VS-mode, if the XLEN for VU-mode is greater than 32, an attempt to -access a high-half user-level CSR (distinct from an unprivileged CSR) -always raises an illegal instruction exception. On the other hand, when -V=1 and XLEN=32, an invalid attempt to access a high-half S-level, -hypervisor, VS, or unprivileged CSR raises a virtual instruction +XLEN=32, an invalid attempt to access a high-half CSR +raises a virtual instruction exception instead of an illegal instruction exception if the same CSR -instruction for the partner _low-half_ CSR (e.g.`cycle` or `htimedelta`) -is HS-qualified. Likewise, in VS-mode, if the XLEN for VU-mode is 32, an -invalid attempt to access a high-half user-level CSR raises a virtual -instruction exception instead of an illegal instruction exception if the -same CSR instruction for the partner low-half CSR is HS-qualified. +instruction for the corresponding _low-half_ CSR (e.g.`cycle` or +`htimedelta`) is HS-qualified. [NOTE] ==== -The RISC-V Privileged Architecture currently defines no user-level CSRs, -but they might be added by a future version of this standard or by an -extension. +When XLEN>32, an attempt to access a high-half CSR +always raises an illegal instruction exception. ==== Specifically, a virtual instruction exception is raised for the diff --git a/src/images/bytefield/mseccfg.adoc b/src/images/bytefield/mseccfg.adoc index 7c8cea1..cdf4803 100644 --- a/src/images/bytefield/mseccfg.adoc +++ b/src/images/bytefield/mseccfg.adoc @@ -4,7 +4,7 @@ (def row-height 45) (def row-header-fn nil) (def boxes-per-row 32) -(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["" "0" "" "1" "" "2" "" "3" "" "7" "" "8" "" "" "9" "" "10" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "XLEN-1"])}) +(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["" "0" "" "1" "" "2" "" "3" "" "7" "" "8" "" "" "9" "" "10" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "63"])}) (draw-box (text "WPRI" {:font-weight "bold"}) {:span 16}) (draw-box "SSEED" {:span 3}) @@ -14,11 +14,11 @@ (draw-box "MMWP" {:span 3}) (draw-box "MML" {:span 2}) -(draw-box "XLEN-10" {:span 16 :borders {}}) +(draw-box "54" {:span 16 :borders {}}) (draw-box "1" {:span 3 :borders {}}) (draw-box "1" {:span 3 :borders {}}) (draw-box "5" {:span 3 :borders {}}) (draw-box "1" {:span 2 :borders {}}) (draw-box "1" {:span 3 :borders {}}) (draw-box "1" {:span 2 :borders {}}) -----
\ No newline at end of file +---- diff --git a/src/machine.adoc b/src/machine.adoc index a2b90a7..6e76b32 100644 --- a/src/machine.adoc +++ b/src/machine.adoc @@ -1394,7 +1394,7 @@ generate an interrupt when a hardware performance monitor counter overflows. ==== -When MXLEN=32, reads of the `mcycle`, `minstret`, and `mhpmcountern` +When XLEN=32, reads of the `mcycle`, `minstret`, and `mhpmcountern` CSRs return bits 31-0 of the corresponding counter, and writes change only bits 31-0; reads of the `mcycleh`, `minstreth`, and `mhpmcounternh` CSRs return bits 63-32 of the corresponding counter, and writes change @@ -1905,14 +1905,14 @@ of a memory-mapped register that is programmed by the platform or by M-mode software towards the beginning of the boot process. ==== -==== Machine Environment Configuration Registers (`menvcfg` and `menvcfgh`) +==== Machine Environment Configuration Register (`menvcfg`) -The `menvcfg` CSR is an MXLEN-bit read/write register, formatted for -MXLEN=64 as shown in [[menvcfg]], that controls +The `menvcfg` CSR is a 64-bit read/write register, formatted +as shown in [[menvcfg]], that controls certain characteristics of the execution environment for modes less privileged than M. -.Machine environment configuration register (`menvcfg`) for MXLEN=64. +.Machine environment configuration register (`menvcfg`). include::images/bytefield/menvcfgreg.adoc[] If bit FIOM (Fence of I/O implies Memory) is set to one in `menvcfg`, @@ -1973,23 +1973,18 @@ The definitions of the CBCFE and CBIE fields will be furnished by the forthcoming Zicbom extension. Their allocations within `menvcfg` may change prior to the ratification of that extension. -When MXLEN=32, `menvcfg` contains the same fields as bits 31:0 of -`menvcfg` when MXLEN=64. Additionally, when MXLEN=32, `menvcfgh` is a -32-bit read/write register that contains the same fields as bits 63:32 -of `menvcfg` when MXLEN=64. Register `menvcfgh` does not exist when -MXLEN=64. +When XLEN=32, `menvcfgh` is a 32-bit read/write register +that aliases bits 63:32 of `menvcfg`. +Register `menvcfgh` does not exist when XLEN=64. If U-mode is not supported, then registers `menvcfg` and `menvcfgh` do not exist. ==== Machine Security Configuration Register (`mseccfg`) -`mseccfg` is an optional MXLEN-bit read/write register, formatted as +`mseccfg` is an optional 64-bit read/write register, formatted as shown in <<mseccfg>>, that controls security features. -When MXLEN=32 only, `mseccfgh` is a 32-bit read/write register that -contains the same fields as `mseccfg` bits 63:32 when MXLEN=64. - [[mseccfg]] .Machine security configuration register (`mseccfg`). include::images/bytefield/mseccfg.adoc[] @@ -2002,6 +1997,10 @@ The definitions of the RLB, MMWP, and MML fields will be furnished by the forthcoming PMP-enhancement extension, Smepmp. Their allocations within `mseccfg` may change prior to the ratification of that extension. +When XLEN=32 only, `mseccfgh` is a 32-bit read/write register that +aliases bits 63:32 of `mseccfg`. +Register `mseccfgh` does not exist when XLEN=64. + === Machine-Level Memory-Mapped Registers ==== Machine Timer Registers (`mtime` and `mtimecmp`) diff --git a/src/priv-csrs.adoc b/src/priv-csrs.adoc index 7b3404e..ae31ade 100644 --- a/src/priv-csrs.adoc +++ b/src/priv-csrs.adoc @@ -490,7 +490,7 @@ HRM |`henvcfg` + `henvcfgh` |Hypervisor environment configuration register. + -Additional hypervisor env. conf. register, RV32 only. + +Upper 32 bits of `henvcfg`, RV32 only. 4+^|Hypervisor Protection and Translation @@ -509,7 +509,7 @@ HRW |`htimedelta` + `htimedeltah` |Delta for VS/VU-mode timer. + -Upper 32 bits of `htimedelta`, HSXLEN=32 only. +Upper 32 bits of `htimedelta`, RV32 only. 4+^|Virtual Supervisor Registers @@ -662,9 +662,9 @@ MRW `mseccfg` + `mseccfgh` |Machine environment configuration register. + -Additional machine env. conf. register, RV32 only. + +Upper 32 bits of `menvcfg`, RV32 only. + Machine security configuration register. + -Additional machine security conf. register, RV32 only. +Upper 32 bits of `mseccfg`, RV32 only. 4+^|Machine Memory Protection @@ -982,3 +982,25 @@ at the same positions in the temporary register. Changing the width of a CSR is not a read or write of the CSR and thus does not trigger any side effects. + +=== Explicit Accesses to CSRs Wider than XLEN + +If a standard CSR is wider than XLEN bits, then an explicit read +of the CSR returns the register's least-significant XLEN bits, +and an explicit write to the CSR modifies only the register's +least-significant XLEN bits, leaving the upper bits unchanged. + +Some standard CSRs, such as the counter CSRs of extension +Zicntr, are always 64 bits, even when XLEN=32 (RV32). +For each such 64-bit CSR (for example, counter `time`), +a corresponding 32-bit _high-half CSR_ is usually defined with +the same name but with the letter '`h`' appended at the end (`timeh`). +The high-half CSR aliases bits 63:32 of its namesake +64-bit CSR, thus providing a way for RV32 software +to read and modify the otherwise-unreachable 32 bits. + +Standard high-half CSRs are accessible only when +the base RISC-V instruction set is RV32 (XLEN=32). +For RV64 (when XLEN=64), the addresses of all standard high-half CSRs +are reserved, so an attempt to access a high-half CSR +typically raises an illegal instruction exception. diff --git a/src/priv-preface.adoc b/src/priv-preface.adoc index 15720e7..e62d59f 100644 --- a/src/priv-preface.adoc +++ b/src/priv-preface.adoc @@ -36,6 +36,7 @@ version 1.12: * Defined the `misa`.V field to reflect that the V extension has been implemented. +* Clarified semantics of explicit accesses to CSRs wider than XLEN bits. *_Preface to Version 20211203_* |