Merge pull request #1025 from damageboy/wavedrom_svg

switch all wavedrom images to output svg

99 files changed, 131 insertions, 131 deletions

diff --git a/src/images/wavedrom/atomic-mem.adoc b/src/images/wavedrom/atomic-mem.adoc
index cb70230..ef66028 100644
--- a/src/images/wavedrom/atomic-mem.adoc
+++ b/src/images/wavedrom/atomic-mem.adoc
@@ -1,6 +1,6 @@
 //## 9.4 Atomic Memory Operations
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode',     type: 8, attr: ['7','AMO','AMO','AMO','AMO','AMO','AMO','AMO']},
diff --git a/src/images/wavedrom/c-andi.adoc b/src/images/wavedrom/c-andi.adoc
index 6b5c3ce..5eca644 100644
--- a/src/images/wavedrom/c-andi.adoc
+++ b/src/images/wavedrom/c-andi.adoc
@@ -1,6 +1,6 @@
 //c-andi.adoc
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2, name: 'op',    type: 5, attr: ['2','C1'],},
diff --git a/src/images/wavedrom/c-breakpoint-instr.adoc b/src/images/wavedrom/c-breakpoint-instr.adoc
index 809fccc..99ae2d5 100644
--- a/src/images/wavedrom/c-breakpoint-instr.adoc
+++ b/src/images/wavedrom/c-breakpoint-instr.adoc
@@ -1,6 +1,6 @@
 //
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 
 ....
 {reg: [
diff --git a/src/images/wavedrom/c-cb-format-ls.adoc b/src/images/wavedrom/c-cb-format-ls.adoc
index 03162f2..daf2248 100644
--- a/src/images/wavedrom/c-cb-format-ls.adoc
+++ b/src/images/wavedrom/c-cb-format-ls.adoc
@@ -1,6 +1,6 @@
 //c-cb-format-ls
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2, name: 'op', type: 8, attr: ['2','C1', 'C1']},
diff --git a/src/images/wavedrom/c-ci.adoc b/src/images/wavedrom/c-ci.adoc
index be8fa56..3651f61 100644
--- a/src/images/wavedrom/c-ci.adoc
+++ b/src/images/wavedrom/c-ci.adoc
@@ -1,6 +1,6 @@
 //
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2, name: 'op', type: 3, attr: ['2', 'C2']},
diff --git a/src/images/wavedrom/c-ciw.adoc b/src/images/wavedrom/c-ciw.adoc
index e737645..3e62efe 100644
--- a/src/images/wavedrom/c-ciw.adoc
+++ b/src/images/wavedrom/c-ciw.adoc
@@ -1,6 +1,6 @@
 //c-ciw.adoc
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2, name: 'op', type: 3, attr: ['2','C0'],},
diff --git a/src/images/wavedrom/c-cj-format-ls.adoc b/src/images/wavedrom/c-cj-format-ls.adoc
index fb37cee..1ecbd35 100644
--- a/src/images/wavedrom/c-cj-format-ls.adoc
+++ b/src/images/wavedrom/c-cj-format-ls.adoc
@@ -10,7 +10,7 @@
 //....
 
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2, name: 'op',     type: 8, attr: ['2','C1','C1']},
diff --git a/src/images/wavedrom/c-cr-format-ls.adoc b/src/images/wavedrom/c-cr-format-ls.adoc
index 66aa318..0329261 100644
--- a/src/images/wavedrom/c-cr-format-ls.adoc
+++ b/src/images/wavedrom/c-cr-format-ls.adoc
@@ -1,6 +1,6 @@
 //These instructions use the CR format.
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2, name: 'op', type: 8, attr: ['2','C2', 'C2']},
diff --git a/src/images/wavedrom/c-cs-format-ls.adoc b/src/images/wavedrom/c-cs-format-ls.adoc
index f39f162..dd9acef 100644
--- a/src/images/wavedrom/c-cs-format-ls.adoc
+++ b/src/images/wavedrom/c-cs-format-ls.adoc
@@ -1,7 +1,7 @@
 //## 16.X Load and Store Instructions
 //### c-cs-format-ls
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2, name: 'op',     type: 8, attr: ['2', 'C0','C0','C0','C0','C0']},
diff --git a/src/images/wavedrom/c-def-illegal-inst.adoc b/src/images/wavedrom/c-def-illegal-inst.adoc
index 494a809..add949d 100644
--- a/src/images/wavedrom/c-def-illegal-inst.adoc
+++ b/src/images/wavedrom/c-def-illegal-inst.adoc
@@ -1,6 +1,6 @@
 //
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 
 ....
 {reg: [
diff --git a/src/images/wavedrom/c-int-reg-immed.adoc b/src/images/wavedrom/c-int-reg-immed.adoc
index a43a59d..a804555 100644
--- a/src/images/wavedrom/c-int-reg-immed.adoc
+++ b/src/images/wavedrom/c-int-reg-immed.adoc
@@ -1,6 +1,6 @@
 //c-int-reg-immed.adoc
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2, name: 'op',        type: 3, attr: ['2','C1', 'C1', 'C1']},
diff --git a/src/images/wavedrom/c-int-reg-to-reg-ca-format.adoc b/src/images/wavedrom/c-int-reg-to-reg-ca-format.adoc
index d5334ae..b2cf982 100644
--- a/src/images/wavedrom/c-int-reg-to-reg-ca-format.adoc
+++ b/src/images/wavedrom/c-int-reg-to-reg-ca-format.adoc
@@ -1,6 +1,6 @@
 //
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 
 ....
 {reg: [
diff --git a/src/images/wavedrom/c-int-reg-to-reg-cr-format.adoc b/src/images/wavedrom/c-int-reg-to-reg-cr-format.adoc
index 0fea241..5e607f8 100644
--- a/src/images/wavedrom/c-int-reg-to-reg-cr-format.adoc
+++ b/src/images/wavedrom/c-int-reg-to-reg-cr-format.adoc
@@ -1,6 +1,6 @@
 //
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 
 ....
 {reg: [
diff --git a/src/images/wavedrom/c-integer-const-gen.adoc b/src/images/wavedrom/c-integer-const-gen.adoc
index 73f46e4..0eaf2d7 100644
--- a/src/images/wavedrom/c-integer-const-gen.adoc
+++ b/src/images/wavedrom/c-integer-const-gen.adoc
@@ -1,6 +1,6 @@
 //c-integer-const-gen
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2, name: 'op', type: 3, attr: ['2','C1', 'C1']},
diff --git a/src/images/wavedrom/c-nop-instr.adoc b/src/images/wavedrom/c-nop-instr.adoc
index 53dbcd7..e3fada1 100644
--- a/src/images/wavedrom/c-nop-instr.adoc
+++ b/src/images/wavedrom/c-nop-instr.adoc
@@ -1,6 +1,6 @@
 //
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 
 ....
 {reg: [
diff --git a/src/images/wavedrom/c-sp-load-store-css.adoc b/src/images/wavedrom/c-sp-load-store-css.adoc
index 4ce8d78..8bbe0d9 100644
--- a/src/images/wavedrom/c-sp-load-store-css.adoc
+++ b/src/images/wavedrom/c-sp-load-store-css.adoc
@@ -1,6 +1,6 @@
 //c-sp load and store, css format--is this correct?
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 1, name: 'op',     type: 8, attr: ['2','C2','C2','C2','C2','C2']},
diff --git a/src/images/wavedrom/c-sp-load-store.adoc b/src/images/wavedrom/c-sp-load-store.adoc
index f07802b..c39f2f6 100644
--- a/src/images/wavedrom/c-sp-load-store.adoc
+++ b/src/images/wavedrom/c-sp-load-store.adoc
@@ -1,7 +1,7 @@
 //## 16.3 Load and Store Instructions
 //### Stack-Pointer-Based Loads and Stores
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2, name: 'op',     type: 8, attr: ['2','C2','C2','C2','C2','C2']},
diff --git a/src/images/wavedrom/c-srli-srai.adoc b/src/images/wavedrom/c-srli-srai.adoc
index 95a2273..7f50c37 100644
--- a/src/images/wavedrom/c-srli-srai.adoc
+++ b/src/images/wavedrom/c-srli-srai.adoc
@@ -1,6 +1,6 @@
 //c-srli-srai.adoc
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2, name: 'op', type: 3, attr: ['2','C1', 'C1'],},
diff --git a/src/images/wavedrom/counters-diag.adoc b/src/images/wavedrom/counters-diag.adoc
index caf8123..8668162 100644
--- a/src/images/wavedrom/counters-diag.adoc
+++ b/src/images/wavedrom/counters-diag.adoc
@@ -1,7 +1,7 @@
 //# 11 Counters
 //## 11.1 Base Counters and Timers
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode', attr: ['7','SYSTEM','SYSTEM','SYSTEM'], type: 8},
diff --git a/src/images/wavedrom/cr-register.adoc b/src/images/wavedrom/cr-register.adoc
index 2039888..f4043d2 100644
--- a/src/images/wavedrom/cr-register.adoc
+++ b/src/images/wavedrom/cr-register.adoc
@@ -3,7 +3,7 @@
 //Table 16.1: Compressed 16-bit RVC instruction formats.
 //### CR : Register
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2, name: 'op',     type: 8},
@@ -13,7 +13,7 @@
   ]}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2, name: 'op',     type: 8},
@@ -24,7 +24,7 @@
 ]}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2, name: 'op',     type: 8},
@@ -34,7 +34,7 @@
 ]}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2, name: 'op',     type: 8},
@@ -44,7 +44,7 @@
 ]}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2, name: 'op',     type: 8},
@@ -56,7 +56,7 @@
 ]}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2, name: 'op',     type: 8},
@@ -68,7 +68,7 @@
 ]}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2, name: 'op',     type: 8},
@@ -79,7 +79,7 @@
 ]}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2, name: 'op',     type: 8},
@@ -90,7 +90,7 @@
 ]}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2,  name: 'op',     type: 8},
diff --git a/src/images/wavedrom/cr-registers-new.adoc b/src/images/wavedrom/cr-registers-new.adoc
index e3e7a23..805b3cb 100644
--- a/src/images/wavedrom/cr-registers-new.adoc
+++ b/src/images/wavedrom/cr-registers-new.adoc
@@ -1,4 +1,4 @@
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 ### CR : Register
 ${wd({reg: [
diff --git a/src/images/wavedrom/csr-instr.adoc b/src/images/wavedrom/csr-instr.adoc
index e09336e..e4a54a5 100644
--- a/src/images/wavedrom/csr-instr.adoc
+++ b/src/images/wavedrom/csr-instr.adoc
@@ -1,7 +1,7 @@
 //# 10 "Zicsr", Control and Status Register (CSR) Instructions, Version 2.0
 //## 10.1 CSR Instructions
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode', attr: ['7', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM'], type: 8},
diff --git a/src/images/wavedrom/ct-conditional.adoc b/src/images/wavedrom/ct-conditional.adoc
index 1ab3f21..84ef7c5 100644
--- a/src/images/wavedrom/ct-conditional.adoc
+++ b/src/images/wavedrom/ct-conditional.adoc
@@ -1,6 +1,6 @@
 //### Conditional Branches
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'BRANCH', 'BRANCH', 'BRANCH'], type: 8},
diff --git a/src/images/wavedrom/ct-unconditional-2.adoc b/src/images/wavedrom/ct-unconditional-2.adoc
index 84760bc..ef33a9e 100644
--- a/src/images/wavedrom/ct-unconditional-2.adoc
+++ b/src/images/wavedrom/ct-unconditional-2.adoc
@@ -1,6 +1,6 @@
 //ct-unconditional-2
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',     attr: ['7', 'JALR'], type: 8},
diff --git a/src/images/wavedrom/ct-unconditional.adoc b/src/images/wavedrom/ct-unconditional.adoc
index 3c72b00..756108f 100644
--- a/src/images/wavedrom/ct-unconditional.adoc
+++ b/src/images/wavedrom/ct-unconditional.adoc
@@ -1,7 +1,7 @@
 //## 2.5 Control Transfer Instructions
 //### Unconditional Jumps
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode', attr: ['7', 'JAL'], type: 8},
diff --git a/src/images/wavedrom/d-xwwx.adoc b/src/images/wavedrom/d-xwwx.adoc
index f48ee15..5965715 100644
--- a/src/images/wavedrom/d-xwwx.adoc
+++ b/src/images/wavedrom/d-xwwx.adoc
@@ -1,6 +1,6 @@
 //xw-wx
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8},
diff --git a/src/images/wavedrom/division-op.adoc b/src/images/wavedrom/division-op.adoc
index 19dd80b..600337d 100644
--- a/src/images/wavedrom/division-op.adoc
+++ b/src/images/wavedrom/division-op.adoc
@@ -1,6 +1,6 @@
 //## 8.2 Division Operations
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode', attr: ['7', 'OP', 'OP'], type: 8},
diff --git a/src/images/wavedrom/double-fl-class.adoc b/src/images/wavedrom/double-fl-class.adoc
index 55fb1ce..143ff5e 100644
--- a/src/images/wavedrom/double-fl-class.adoc
+++ b/src/images/wavedrom/double-fl-class.adoc
@@ -1,6 +1,6 @@
 //## 13.7 Double-Precision Floating-Point Classify Instruction
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8},
diff --git a/src/images/wavedrom/double-fl-compare.adoc b/src/images/wavedrom/double-fl-compare.adoc
index 7e6118e..8403734 100644
--- a/src/images/wavedrom/double-fl-compare.adoc
+++ b/src/images/wavedrom/double-fl-compare.adoc
@@ -1,6 +1,6 @@
 //## 13.6 Double-Precision Floating-Point Compare Instructions
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8},
diff --git a/src/images/wavedrom/double-fl-compute.adoc b/src/images/wavedrom/double-fl-compute.adoc
index 45f9ac7..4ce3b71 100644
--- a/src/images/wavedrom/double-fl-compute.adoc
+++ b/src/images/wavedrom/double-fl-compute.adoc
@@ -1,6 +1,6 @@
 //## 13.4 Double-Precision Floating-Point Computational Instructions
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP'], type: 8},
@@ -13,7 +13,7 @@
 ]}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB'],    type: 8},
diff --git a/src/images/wavedrom/double-fl-convert-mv.adoc b/src/images/wavedrom/double-fl-convert-mv.adoc
index b396961..fb23b08 100644
--- a/src/images/wavedrom/double-fl-convert-mv.adoc
+++ b/src/images/wavedrom/double-fl-convert-mv.adoc
@@ -1,7 +1,7 @@
 //## 13.5 Double-Precision Floating-Point Conversion and Move Instructions
 
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8},
diff --git a/src/images/wavedrom/double-ls.adoc b/src/images/wavedrom/double-ls.adoc
index 9b76327..0c6f4dd 100644
--- a/src/images/wavedrom/double-ls.adoc
+++ b/src/images/wavedrom/double-ls.adoc
@@ -1,7 +1,7 @@
 //# "D" Standard Extension for Double-Precision Floating-Point, Version 2.2
 //## 13.3 Double-Precision Load and Store Instructions
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7','LOAD-FP'],  type: 8},
@@ -12,7 +12,7 @@
 ]}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7','STORE-FP'], type: 8},
diff --git a/src/images/wavedrom/env_call-breakpoint.adoc b/src/images/wavedrom/env_call-breakpoint.adoc
index a41d7b6..7812687 100644
--- a/src/images/wavedrom/env_call-breakpoint.adoc
+++ b/src/images/wavedrom/env_call-breakpoint.adoc
@@ -1,6 +1,6 @@
 //## 2.8 Environment Call and Breakpoints
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'SYSTEM', 'SYSTEM'], type: 8},
diff --git a/src/images/wavedrom/fcvt-sd-ds.adoc b/src/images/wavedrom/fcvt-sd-ds.adoc
index d03abdc..5b68a54 100644
--- a/src/images/wavedrom/fcvt-sd-ds.adoc
+++ b/src/images/wavedrom/fcvt-sd-ds.adoc
@@ -1,6 +1,6 @@
 //FCVT.S.D and FCVT.D.S
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8},
diff --git a/src/images/wavedrom/float-csr.adoc b/src/images/wavedrom/float-csr.adoc
index 2e7b6b8..7b2cf24 100644
--- a/src/images/wavedrom/float-csr.adoc
+++ b/src/images/wavedrom/float-csr.adoc
@@ -2,7 +2,7 @@
 //## 12.2 Floating-Point Control and Status Register
 //### Figure 12.2: Floating-point control and status register.
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 1,  name: 'NX', attr: ['1'], type: 5},
diff --git a/src/images/wavedrom/flt-pt-to-int-move.adoc b/src/images/wavedrom/flt-pt-to-int-move.adoc
index e99e73d..fc2a95a 100644
--- a/src/images/wavedrom/flt-pt-to-int-move.adoc
+++ b/src/images/wavedrom/flt-pt-to-int-move.adoc
@@ -1,6 +1,6 @@
 // 16.3 Instructions for moving bit patterns between floating-point and integer registers.
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'],  type: 8},
diff --git a/src/images/wavedrom/flt-to-flt-sgn-inj-instr.adoc b/src/images/wavedrom/flt-to-flt-sgn-inj-instr.adoc
index 00a6d2a..43250a4 100644
--- a/src/images/wavedrom/flt-to-flt-sgn-inj-instr.adoc
+++ b/src/images/wavedrom/flt-to-flt-sgn-inj-instr.adoc
@@ -1,6 +1,6 @@
 // 16.3 Floating point to floating point sign injection instructions.
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP'],  type: 8},
diff --git a/src/images/wavedrom/fnmaddsub.adoc b/src/images/wavedrom/fnmaddsub.adoc
index 97038ac..e8bda1b 100644
--- a/src/images/wavedrom/fnmaddsub.adoc
+++ b/src/images/wavedrom/fnmaddsub.adoc
@@ -1,7 +1,7 @@
 
 //FNMSUP and FNMADD
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB'],    type: 8},
diff --git a/src/images/wavedrom/fsjgnjnx-d.adoc b/src/images/wavedrom/fsjgnjnx-d.adoc
index ab861a4..fff7808 100644
--- a/src/images/wavedrom/fsjgnjnx-d.adoc
+++ b/src/images/wavedrom/fsjgnjnx-d.adoc
@@ -1,6 +1,6 @@
 //FSGNJ.D, FSGNJN.D, and FSGNJX.D
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8},
diff --git a/src/images/wavedrom/half-ls.adoc b/src/images/wavedrom/half-ls.adoc
index cf9bddd..fb26d9b 100644
--- a/src/images/wavedrom/half-ls.adoc
+++ b/src/images/wavedrom/half-ls.adoc
@@ -1,6 +1,6 @@
 //## 15.1 Half-Precision Load and Store Instructions
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: 'LOAD-FP',  type: 8},
diff --git a/src/images/wavedrom/half-pr-flt-pt-class.adoc b/src/images/wavedrom/half-pr-flt-pt-class.adoc
index 13356be..5490f5e 100644
--- a/src/images/wavedrom/half-pr-flt-pt-class.adoc
+++ b/src/images/wavedrom/half-pr-flt-pt-class.adoc
@@ -1,6 +1,6 @@
 //## 15.5 Half-Precision Floating-Point Classify Instruction
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7', 'OP-FP'],  type: 8},
diff --git a/src/images/wavedrom/half-pr-flt-pt-compare.adoc b/src/images/wavedrom/half-pr-flt-pt-compare.adoc
index 302c9d2..78033c1 100644
--- a/src/images/wavedrom/half-pr-flt-pt-compare.adoc
+++ b/src/images/wavedrom/half-pr-flt-pt-compare.adoc
@@ -1,6 +1,6 @@
 // 16.4 Half-Precision Floating-Point Compare Instructions.
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP'],  type: 8},
diff --git a/src/images/wavedrom/half-prec-conv-and-mv.adoc b/src/images/wavedrom/half-prec-conv-and-mv.adoc
index 01ac36a..013f1b9 100644
--- a/src/images/wavedrom/half-prec-conv-and-mv.adoc
+++ b/src/images/wavedrom/half-prec-conv-and-mv.adoc
@@ -1,7 +1,7 @@
 //## 16.3 Half-Precision Conversion and Move Instructions
 
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7','OP-FP','OP-FP'],  type: 8},
diff --git a/src/images/wavedrom/half-prec-flpt-to-flpt-conv.adoc b/src/images/wavedrom/half-prec-flpt-to-flpt-conv.adoc
index caec555..c42038c 100644
--- a/src/images/wavedrom/half-prec-flpt-to-flpt-conv.adoc
+++ b/src/images/wavedrom/half-prec-flpt-to-flpt-conv.adoc
@@ -1,6 +1,6 @@
 //## 16.3 Half-Precision Floating Point to Floating Point Conversion Instructions
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP','OP-FP','OP-FP'],  type: 8},
diff --git a/src/images/wavedrom/half-store.adoc b/src/images/wavedrom/half-store.adoc
index d72b7a6..fb0d18c 100644
--- a/src/images/wavedrom/half-store.adoc
+++ b/src/images/wavedrom/half-store.adoc
@@ -1,4 +1,4 @@
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: 'STORE-FP', type: 8},
diff --git a/src/images/wavedrom/hint-nopv_rv32i.adoc b/src/images/wavedrom/hint-nopv_rv32i.adoc
index eda6dcb..b26a6d1 100644
--- a/src/images/wavedrom/hint-nopv_rv32i.adoc
+++ b/src/images/wavedrom/hint-nopv_rv32i.adoc
@@ -1,7 +1,7 @@
 //### RV32I
 //These instructions reserved as HINTs in the latest spec: https://github.com/riscv/riscv-isa-manual/releases (2.9)
 //{ADDI, SLTI, SLTIU, XORI, ORI, ANDI} x0, ? ( ${ 6 * 1 << 17} )
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
     {name: 'OP-IMM', bits: 7, attr: 0b0010011},
@@ -12,7 +12,7 @@
 ....
 //{SLLI, SRLI, SRAI} x0, ? ( ${ 3 * 1 << 10} )
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg:[
     {name: 'OP-IMM', bits: 7, attr: 0b0010011},
@@ -24,7 +24,7 @@
 ....
 //{LUI, AUIPC} x0, ? ( ${ 2 * (1 << 20) } )
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg:[
     {name: 'opcode', bits: 7,  attr: ['AUIPC', 'LUI']},
@@ -34,7 +34,7 @@
 ....
 //{ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND} x0, ?, ? ( ${ 10 * 1 << 10} )
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg:[
     {name: 'OP',     bits: 7, attr: 0b0110011},
diff --git a/src/images/wavedrom/hint-nopv_rv64i.adoc b/src/images/wavedrom/hint-nopv_rv64i.adoc
index 6ec83cb..ee78cf8 100644
--- a/src/images/wavedrom/hint-nopv_rv64i.adoc
+++ b/src/images/wavedrom/hint-nopv_rv64i.adoc
@@ -2,7 +2,7 @@
 //These instructions reserved as HINTs in the latest spec: https://github.com/riscv/riscv-isa-manual/releases (4.4)
 //All RV32I NOPs plus:
 //ADDIW x0, ? ( ${ 1 << 17 } )
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg:[
     {name: 'OP-IMM-32', bits: 7,  attr: 0b0011011},
@@ -14,7 +14,7 @@
 //Extra bit for the shift ammont:
 //{SLLI, SRLI, SRAI} x0, ? ( ${ 3 * 1 << 10} )
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
     {name: 'OP-IMM', bits: 7, attr: 0b0010011},
@@ -26,7 +26,7 @@
 ....
 //{SLLIW, SRLIW, SRAIW} x0, ?( ${ 3 * 1 << 10} )
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg:[
     {name: 'OP-IMM-32', bits: 7,  attr: 0b0011011},
@@ -39,7 +39,7 @@
 //SLL, SLT, SRA ( ??? )
 //{ADDW, SLLW, SRLW, SUBW, SRAW} x0, ?, ? ( ${ 5 * 1 << 10 } )
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg:[
     {name: 'OP-32', bits: 7,  attr: 0b0111011},
diff --git a/src/images/wavedrom/hinvalgvma.edn b/src/images/wavedrom/hinvalgvma.edn
index 4a2c3fd..ab1a0cd 100644
--- a/src/images/wavedrom/hinvalgvma.edn
+++ b/src/images/wavedrom/hinvalgvma.edn
@@ -1,4 +1,4 @@
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'SYSTEM'],  type: 8},
diff --git a/src/images/wavedrom/hinvalvvma.edn b/src/images/wavedrom/hinvalvvma.edn
index cf4c2d1..0b93b9f 100644
--- a/src/images/wavedrom/hinvalvvma.edn
+++ b/src/images/wavedrom/hinvalvvma.edn
@@ -1,4 +1,4 @@
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'SYSTEM'],  type: 8},
diff --git a/src/images/wavedrom/hypv-mm-fence.edn b/src/images/wavedrom/hypv-mm-fence.edn
index 791ee99..2840b1a 100644
--- a/src/images/wavedrom/hypv-mm-fence.edn
+++ b/src/images/wavedrom/hypv-mm-fence.edn
@@ -1,6 +1,6 @@
 //hypv-mm-fence.edn
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode',    type: 3, attr: ['7', 'SYSTEM', 'SYSTEM']},
diff --git a/src/images/wavedrom/hypv-virt-load-and-store.edn b/src/images/wavedrom/hypv-virt-load-and-store.edn
index 78051a5..d0e1d9e 100644
--- a/src/images/wavedrom/hypv-virt-load-and-store.edn
+++ b/src/images/wavedrom/hypv-virt-load-and-store.edn
@@ -1,6 +1,6 @@
 //hypv-virt-load-and-store.edn
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode',    type: 3, attr: ['7','SYSTEM', 'SYSTEM', 'SYSTEM']},
diff --git a/src/images/wavedrom/immediate.adoc b/src/images/wavedrom/immediate.adoc
index 1032f80..c6fb00d 100644
--- a/src/images/wavedrom/immediate.adoc
+++ b/src/images/wavedrom/immediate.adoc
@@ -2,7 +2,7 @@
 //Types of immediate produced by RISC-V instructions. The fields are labeled with the instruction bits used to construct their value. Sign extension always uses inst[31].
 //#### I-immediate
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 1,  name: '[20]'},
@@ -13,7 +13,7 @@
 ....
 //#### S-immediate
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 1,  name: '[7]'},
@@ -24,7 +24,7 @@
 ....
 //#### B-immediate
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 1,  name: '0', type: 5},
@@ -36,7 +36,7 @@
 ....
 //#### U-immediate
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 12, name: '0', type: 5},
@@ -47,7 +47,7 @@
 ....
 //#### J-immediate
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 1,  name: '0', type: 5},
diff --git a/src/images/wavedrom/immediate_variants.adoc b/src/images/wavedrom/immediate_variants.adoc
index 6a769b5..c1f8335 100644
--- a/src/images/wavedrom/immediate_variants.adoc
+++ b/src/images/wavedrom/immediate_variants.adoc
@@ -2,7 +2,7 @@
 //### Figure 2.3
 //RISC-V base instruction formats showing immediate variants.
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode'},
@@ -14,7 +14,7 @@
 ], config: {label: {right: 'R-Type'}}}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode'},
@@ -25,7 +25,7 @@
 ], config: {label: {right: 'I-Type'}}}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode'},
@@ -37,7 +37,7 @@
 ], config: {label: {right: 'S-Type'}}}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode'},
@@ -51,7 +51,7 @@
 ], config: {fontsize: 12, label: {right: 'B-Type'}}}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode'},
@@ -60,7 +60,7 @@
 ], config: {label: {right: 'U-Type'}}}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode'},
diff --git a/src/images/wavedrom/instruction_formats.adoc b/src/images/wavedrom/instruction_formats.adoc
index 97c4512..442e27d 100644
--- a/src/images/wavedrom/instruction_formats.adoc
+++ b/src/images/wavedrom/instruction_formats.adoc
@@ -2,7 +2,7 @@
 
 //RISC-V base instruction formats. Each immediate subfield is labeled with the bit position (imm[x]) in the immediate value being produced, rather than the bit position within the instruction’s immediate field as is usually done.
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode', type: 8},
@@ -14,7 +14,7 @@
 ], config: {label: {right: 'R-Type'}}}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode', type: 8},
@@ -25,7 +25,7 @@
 ], config: {label: {right: 'I-Type'}}}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode', type: 8},
@@ -37,7 +37,7 @@
 ], config: {label: {right: 'S-Type'}}}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode', type: 8},
diff --git a/src/images/wavedrom/int-comp-lui-aiupc.adoc b/src/images/wavedrom/int-comp-lui-aiupc.adoc
index c55cd2d..c3dbf95 100644
--- a/src/images/wavedrom/int-comp-lui-aiupc.adoc
+++ b/src/images/wavedrom/int-comp-lui-aiupc.adoc
@@ -2,7 +2,7 @@
 //### Integer Register-Immediate Instructions
 //lui-aiupc-u-immed
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',     attr: ['7', 'LUI', 'AUIPC'], type: 8},
diff --git a/src/images/wavedrom/int-comp-slli-srli-srai.adoc b/src/images/wavedrom/int-comp-slli-srli-srai.adoc
index 9a1e757..3fa49a4 100644
--- a/src/images/wavedrom/int-comp-slli-srli-srai.adoc
+++ b/src/images/wavedrom/int-comp-slli-srli-srai.adoc
@@ -2,7 +2,7 @@
 //### Integer Register-Immediate Instructions
 //
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'OP-IMM', 'OP-IMM', 'OP-IMM'], type: 8},
diff --git a/src/images/wavedrom/int_reg-reg.adoc b/src/images/wavedrom/int_reg-reg.adoc
index b076302..1ec0c17 100644
--- a/src/images/wavedrom/int_reg-reg.adoc
+++ b/src/images/wavedrom/int_reg-reg.adoc
@@ -1,6 +1,6 @@
 //### Integer Register-Register Operations
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'OP', 'OP', 'OP', 'OP'], type: 8},
diff --git a/src/images/wavedrom/integer_computational.adoc b/src/images/wavedrom/integer_computational.adoc
index 898302f..5172d4e 100644
--- a/src/images/wavedrom/integer_computational.adoc
+++ b/src/images/wavedrom/integer_computational.adoc
@@ -1,7 +1,7 @@
 //## 2.4 Integer Computational Instructions
 //### Integer Register-Immediate Instructions
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'OP-IMM', 'OP-IMM'], type: 8},
diff --git a/src/images/wavedrom/load-reserve-st-conditional.adoc b/src/images/wavedrom/load-reserve-st-conditional.adoc
index e4a7c57..67ce56a 100644
--- a/src/images/wavedrom/load-reserve-st-conditional.adoc
+++ b/src/images/wavedrom/load-reserve-st-conditional.adoc
@@ -2,7 +2,7 @@
 //## 9.2 Load-Reserved/Store-Conditional Instructions
 
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'AMO', 'AMO'], type: 8},
diff --git a/src/images/wavedrom/load_store.adoc b/src/images/wavedrom/load_store.adoc
index 62cff4e..f9de4d1 100644
--- a/src/images/wavedrom/load_store.adoc
+++ b/src/images/wavedrom/load_store.adoc
@@ -1,6 +1,6 @@
 //## 2.6 Load and Store Instructions
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'LOAD'], type: 8},
@@ -11,7 +11,7 @@
 ]}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',   attr: ['7', 'STORE'], type: 8},
diff --git a/src/images/wavedrom/m-st-ext-for-int-mult.adoc b/src/images/wavedrom/m-st-ext-for-int-mult.adoc
index c7aca26..520951c 100644
--- a/src/images/wavedrom/m-st-ext-for-int-mult.adoc
+++ b/src/images/wavedrom/m-st-ext-for-int-mult.adoc
@@ -1,7 +1,7 @@
 //# 8 "M" Standard Extension for Integer Multiplication and Division, Version 2.0
 //## 8.1 Multiplication Operations
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode', attr: ['7', 'OP', 'OP-32'], type: 8},
diff --git a/src/images/wavedrom/mm-env-call.adoc b/src/images/wavedrom/mm-env-call.adoc
index f5a4768..9838230 100644
--- a/src/images/wavedrom/mm-env-call.adoc
+++ b/src/images/wavedrom/mm-env-call.adoc
@@ -1,6 +1,6 @@
 //
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 
 ....
 {reg: [
diff --git a/src/images/wavedrom/nop.adoc b/src/images/wavedrom/nop.adoc
index 1dcd3fa..34ad70e 100644
--- a/src/images/wavedrom/nop.adoc
+++ b/src/images/wavedrom/nop.adoc
@@ -1,5 +1,5 @@
 //### NOP Instruction
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'OP-IMM'], type: 8},
diff --git a/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc b/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc
index bfce067..ba4e224 100644
--- a/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc
+++ b/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc
@@ -1,6 +1,6 @@
 //quad-cnvrt-intch-xqqx
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8},
diff --git a/src/images/wavedrom/quad-cnvrt-mv.adoc b/src/images/wavedrom/quad-cnvrt-mv.adoc
index a97999c..3fc9f86 100644
--- a/src/images/wavedrom/quad-cnvrt-mv.adoc
+++ b/src/images/wavedrom/quad-cnvrt-mv.adoc
@@ -1,6 +1,6 @@
 //## 14.3 Quad-Precision Convert and Move Instructions
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8},
diff --git a/src/images/wavedrom/quad-cnvt-interchange.adoc b/src/images/wavedrom/quad-cnvt-interchange.adoc
index 21a511a..1178397 100644
--- a/src/images/wavedrom/quad-cnvt-interchange.adoc
+++ b/src/images/wavedrom/quad-cnvt-interchange.adoc
@@ -1,6 +1,6 @@
 //14 conv-mv
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7', 'OP-FP', 'OP-FP','OP-FP','OP-FP'], type: 8},
diff --git a/src/images/wavedrom/quad-compute.adoc b/src/images/wavedrom/quad-compute.adoc
index 656d99a..6aa3953 100644
--- a/src/images/wavedrom/quad-compute.adoc
+++ b/src/images/wavedrom/quad-compute.adoc
@@ -1,6 +1,6 @@
 //## 14.2 Quad-Precision Computational Instructions
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP'], type: 8},
@@ -13,7 +13,7 @@
 ]}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB'], type: 8},
diff --git a/src/images/wavedrom/quad-float-clssfy.adoc b/src/images/wavedrom/quad-float-clssfy.adoc
index 7143649..0023c7d 100644
--- a/src/images/wavedrom/quad-float-clssfy.adoc
+++ b/src/images/wavedrom/quad-float-clssfy.adoc
@@ -1,6 +1,6 @@
 //## 14.5 Quad-Precision Floating-Point Classify Instruction
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8},
diff --git a/src/images/wavedrom/quad-float-compare.adoc b/src/images/wavedrom/quad-float-compare.adoc
index 8a3d2bb..2269bc9 100644
--- a/src/images/wavedrom/quad-float-compare.adoc
+++ b/src/images/wavedrom/quad-float-compare.adoc
@@ -1,6 +1,6 @@
 //## 14.4 Quad-Precision Floating-Point Compare Instructions
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8},
diff --git a/src/images/wavedrom/quad-ls.adoc b/src/images/wavedrom/quad-ls.adoc
index 4e87ea7..3ba4099 100644
--- a/src/images/wavedrom/quad-ls.adoc
+++ b/src/images/wavedrom/quad-ls.adoc
@@ -1,6 +1,6 @@
 //## 14.1 Quad-Precision Load and Store Instructions
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7','LOAD-FP'],  type: 8},
@@ -11,7 +11,7 @@
 ]}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7','STORE-FP'], type: 8},
diff --git a/src/images/wavedrom/reg-based-ldnstr.adoc b/src/images/wavedrom/reg-based-ldnstr.adoc
index d81417e..57c04c4 100644
--- a/src/images/wavedrom/reg-based-ldnstr.adoc
+++ b/src/images/wavedrom/reg-based-ldnstr.adoc
@@ -1,7 +1,7 @@
 //Register-Based loads and Stores
 
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 2, name: 'op', attr: ['2', 'C0', 'C0', 'C0', 'C0', 'C0'], type: 8},
diff --git a/src/images/wavedrom/rv64_lui-auipc.adoc b/src/images/wavedrom/rv64_lui-auipc.adoc
index e2f3d5c..132c770 100644
--- a/src/images/wavedrom/rv64_lui-auipc.adoc
+++ b/src/images/wavedrom/rv64_lui-auipc.adoc
@@ -1,6 +1,6 @@
 //lui-auipc
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',     attr: ['7', 'LUI', 'AUIPC'], type: 8},
diff --git a/src/images/wavedrom/rv64i-base-int.adoc b/src/images/wavedrom/rv64i-base-int.adoc
index 503489f..e4edaf3 100644
--- a/src/images/wavedrom/rv64i-base-int.adoc
+++ b/src/images/wavedrom/rv64i-base-int.adoc
@@ -2,7 +2,7 @@
 //## 6.2 Integer Computational Instructions
 //### Integer Register-Immediate Instructions
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'OP-IMM-32'], type: 8},
diff --git a/src/images/wavedrom/rv64i-slli.adoc b/src/images/wavedrom/rv64i-slli.adoc
index 57eff4b..038a052 100644
--- a/src/images/wavedrom/rv64i-slli.adoc
+++ b/src/images/wavedrom/rv64i-slli.adoc
@@ -1,4 +1,4 @@
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'OP-IMM', 'OP-IMM', 'OP-IMM'], type: 8},
diff --git a/src/images/wavedrom/rv64i-slliw.adoc b/src/images/wavedrom/rv64i-slliw.adoc
index e4cda61..bd51e9b 100644
--- a/src/images/wavedrom/rv64i-slliw.adoc
+++ b/src/images/wavedrom/rv64i-slliw.adoc
@@ -1,4 +1,4 @@
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'OP-IMM-32', 'OP-IMM-32', 'OP-IMM-32'], type: 8},
diff --git a/src/images/wavedrom/rv64i_int-reg-reg.adoc b/src/images/wavedrom/rv64i_int-reg-reg.adoc
index 87c0c35..a69e718 100644
--- a/src/images/wavedrom/rv64i_int-reg-reg.adoc
+++ b/src/images/wavedrom/rv64i_int-reg-reg.adoc
@@ -2,7 +2,7 @@
 //rv64i int-reg-reg
 //### Integer Register-Register Operations
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'OP', 'OP', 'OP-32', 'OP-32', 'OP-32'], type: 8},
diff --git a/src/images/wavedrom/sfenceinvalir.edn b/src/images/wavedrom/sfenceinvalir.edn
index 2516a14..639be34 100644
--- a/src/images/wavedrom/sfenceinvalir.edn
+++ b/src/images/wavedrom/sfenceinvalir.edn
@@ -1,4 +1,4 @@
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'SYSTEM'],  type: 8},
diff --git a/src/images/wavedrom/sfencevma.edn b/src/images/wavedrom/sfencevma.edn
index 118e6b3..50225c6 100644
--- a/src/images/wavedrom/sfencevma.edn
+++ b/src/images/wavedrom/sfencevma.edn
@@ -1,4 +1,4 @@
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'SYSTEM'],  type: 8},
diff --git a/src/images/wavedrom/sfencewinval.edn b/src/images/wavedrom/sfencewinval.edn
index b9e87bb..2973af8 100644
--- a/src/images/wavedrom/sfencewinval.edn
+++ b/src/images/wavedrom/sfencewinval.edn
@@ -1,4 +1,4 @@
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'SYSTEM'],  type: 8},
diff --git a/src/images/wavedrom/sinvalvma.edn b/src/images/wavedrom/sinvalvma.edn
index cf913c8..89d0d40 100644
--- a/src/images/wavedrom/sinvalvma.edn
+++ b/src/images/wavedrom/sinvalvma.edn
@@ -1,4 +1,4 @@
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'SYSTEM'],  type: 8},
diff --git a/src/images/wavedrom/sp-load-store.adoc b/src/images/wavedrom/sp-load-store.adoc
index 07716ac..192626b 100644
--- a/src/images/wavedrom/sp-load-store.adoc
+++ b/src/images/wavedrom/sp-load-store.adoc
@@ -1,6 +1,6 @@
 //## 12.5 Single-Precision Load and Store Instructions
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'LOAD-FP'],  type: 8},
@@ -11,7 +11,7 @@
 ]}
 ....
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'STORE-FP'], type: 8},
diff --git a/src/images/wavedrom/spfloat-classify.adoc b/src/images/wavedrom/spfloat-classify.adoc
index 5d83b1e..236880d 100644
--- a/src/images/wavedrom/spfloat-classify.adoc
+++ b/src/images/wavedrom/spfloat-classify.adoc
@@ -1,6 +1,6 @@
 //## 12.9 Single-Precision Floating-Point Classify Instruction
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP'],  type: 8},
diff --git a/src/images/wavedrom/spfloat-cn-cmp.adoc b/src/images/wavedrom/spfloat-cn-cmp.adoc
index 3f4e572..e46a099 100644
--- a/src/images/wavedrom/spfloat-cn-cmp.adoc
+++ b/src/images/wavedrom/spfloat-cn-cmp.adoc
@@ -1,6 +1,6 @@
 //sp float convert and compare
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP', 'OP-FP'],        type: 8},
diff --git a/src/images/wavedrom/spfloat-comp.adoc b/src/images/wavedrom/spfloat-comp.adoc
index 23fd136..7059e8e 100644
--- a/src/images/wavedrom/spfloat-comp.adoc
+++ b/src/images/wavedrom/spfloat-comp.adoc
@@ -1,6 +1,6 @@
 //## 12.8 Single-Precision Floating-Point Compare Instructions
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP'],  type: 8},
diff --git a/src/images/wavedrom/spfloat-mv.adoc b/src/images/wavedrom/spfloat-mv.adoc
index 772589e..d5df81d 100644
--- a/src/images/wavedrom/spfloat-mv.adoc
+++ b/src/images/wavedrom/spfloat-mv.adoc
@@ -1,6 +1,6 @@
 //SP flating point move
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'],    type: 8},
diff --git a/src/images/wavedrom/spfloat-sign-inj.adoc b/src/images/wavedrom/spfloat-sign-inj.adoc
index ba0a94a..74040b7 100644
--- a/src/images/wavedrom/spfloat-sign-inj.adoc
+++ b/src/images/wavedrom/spfloat-sign-inj.adoc
@@ -1,6 +1,6 @@
 //sp float sign injection
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP'],        type: 8},
diff --git a/src/images/wavedrom/spfloat-zfh.adoc b/src/images/wavedrom/spfloat-zfh.adoc
index 1a05317..d53e6bd 100644
--- a/src/images/wavedrom/spfloat-zfh.adoc
+++ b/src/images/wavedrom/spfloat-zfh.adoc
@@ -1,6 +1,6 @@
 //## 12.6 Single-Precision Floating-Point Computational Instructions for ZFH Chapter
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP'],    type: 8},
diff --git a/src/images/wavedrom/spfloat.adoc b/src/images/wavedrom/spfloat.adoc
index e464dbd..9384544 100644
--- a/src/images/wavedrom/spfloat.adoc
+++ b/src/images/wavedrom/spfloat.adoc
@@ -1,6 +1,6 @@
 //## 12.6 Single-Precision Floating-Point Computational Instructions
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP'],    type: 8},
diff --git a/src/images/wavedrom/spfloat2-zfh.adoc b/src/images/wavedrom/spfloat2-zfh.adoc
index 209c4ee..44789da 100644
--- a/src/images/wavedrom/spfloat2-zfh.adoc
+++ b/src/images/wavedrom/spfloat2-zfh.adoc
@@ -1,4 +1,4 @@
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB'],    type: 8},
diff --git a/src/images/wavedrom/spfloat2.adoc b/src/images/wavedrom/spfloat2.adoc
index 974966e..8c2b976 100644
--- a/src/images/wavedrom/spfloat2.adoc
+++ b/src/images/wavedrom/spfloat2.adoc
@@ -1,4 +1,4 @@
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB'],    type: 8},
diff --git a/src/images/wavedrom/transformedatomicinst.edn b/src/images/wavedrom/transformedatomicinst.edn
index 8775b8f..d598bc3 100644
--- a/src/images/wavedrom/transformedatomicinst.edn
+++ b/src/images/wavedrom/transformedatomicinst.edn
@@ -1,4 +1,4 @@
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', type: 8, attr: ['7']},
diff --git a/src/images/wavedrom/transformedloadinst.edn b/src/images/wavedrom/transformedloadinst.edn
index 58ae27b..0d6e5ab 100644
--- a/src/images/wavedrom/transformedloadinst.edn
+++ b/src/images/wavedrom/transformedloadinst.edn
@@ -1,4 +1,4 @@
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', type: 8, attr: ['7']},
diff --git a/src/images/wavedrom/transformedstoreinst.edn b/src/images/wavedrom/transformedstoreinst.edn
index afb5fd2..e807ad5 100644
--- a/src/images/wavedrom/transformedstoreinst.edn
+++ b/src/images/wavedrom/transformedstoreinst.edn
@@ -1,4 +1,4 @@
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', type: 8, attr: ['7']},
diff --git a/src/images/wavedrom/transformedvmaccessinst.edn b/src/images/wavedrom/transformedvmaccessinst.edn
index 6c16f5f..9c7e9e3 100644
--- a/src/images/wavedrom/transformedvmaccessinst.edn
+++ b/src/images/wavedrom/transformedvmaccessinst.edn
@@ -1,4 +1,4 @@
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7, name: 'opcode', type: 8, attr: ['7']},
diff --git a/src/images/wavedrom/trap-return.adoc b/src/images/wavedrom/trap-return.adoc
index b0c0dd4..1e15e2b 100644
--- a/src/images/wavedrom/trap-return.adoc
+++ b/src/images/wavedrom/trap-return.adoc
@@ -1,6 +1,6 @@
 //
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 
 ....
 {reg: [
diff --git a/src/images/wavedrom/wfi.adoc b/src/images/wavedrom/wfi.adoc
index 30c6085..4447b9f 100644
--- a/src/images/wavedrom/wfi.adoc
+++ b/src/images/wavedrom/wfi.adoc
@@ -1,6 +1,6 @@
 //
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 
 ....
 {reg: [
diff --git a/src/images/wavedrom/zifencei-fetch.adoc b/src/images/wavedrom/zifencei-fetch.adoc
index d9cde80..42e0d6f 100644
--- a/src/images/wavedrom/zifencei-fetch.adoc
+++ b/src/images/wavedrom/zifencei-fetch.adoc
@@ -1,6 +1,6 @@
 //# 3 "Zifencei" Instruction-Fetch Fence, Version 2.0
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: 'MISC-MEM', type: 8},
diff --git a/src/images/wavedrom/zifencei-ff.adoc b/src/images/wavedrom/zifencei-ff.adoc
index d6c8068..5ccfae0 100644
--- a/src/images/wavedrom/zifencei-ff.adoc
+++ b/src/images/wavedrom/zifencei-ff.adoc
@@ -1,6 +1,6 @@
 //# 3 "Zifencei" Instruction-Fetch Fence, Version 2.0
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'MISC-MEM'], type: 8},
diff --git a/src/images/wavedrom/zihintpause-hint.adoc b/src/images/wavedrom/zihintpause-hint.adoc
index af8ce65..4c4a2ed 100644
--- a/src/images/wavedrom/zihintpause-hint.adoc
+++ b/src/images/wavedrom/zihintpause-hint.adoc
@@ -1,6 +1,6 @@
 //# 4 "Zihintpause" Pause Hint, Version 1.0
 
-[wavedrom, ,]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: 'MISC-MEM', type: 8},