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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-11-06 14:46:17 -0800 |
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| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-11-06 14:46:17 -0800 |
| commit | efa2a40a2329717142cb975d93c7b3f6ab473295 (patch) | |
| tree | f6eec9adac87335e7f4ae819bcd1c293d6cdc890 | |
| parent | 25358c650b145cf9951601d197856cb5a84ec86e (diff) | |
| download | riscv-isa-manual-efa2a40a2329717142cb975d93c7b3f6ab473295.zip riscv-isa-manual-efa2a40a2329717142cb975d93c7b3f6ab473295.tar.gz riscv-isa-manual-efa2a40a2329717142cb975d93c7b3f6ab473295.tar.bz2 | |
Gave CSR instruction module a name and a version, and made clear these are being ratified also.
| -rw-r--r-- | src/csr.tex | 2 | ||||
| -rw-r--r-- | src/preface.tex | 7 |
2 files changed, 5 insertions, 4 deletions
diff --git a/src/csr.tex b/src/csr.tex index 932b450..8c1b923 100644 --- a/src/csr.tex +++ b/src/csr.tex @@ -1,4 +1,4 @@ -\chapter{Control and Status Register (CSR) Instructions} +\chapter{``Zicsr'', Control and Status Register (CSR) Instructions, Version 2.0} \label{csrinsts} RISC-V defines a separate address space of 4096 Control and Status diff --git a/src/preface.tex b/src/preface.tex index f529285..a400599 100644 --- a/src/preface.tex +++ b/src/preface.tex @@ -31,6 +31,7 @@ modules marked {\em Draft} are expected to change before ratification. Extension & Version & Status \\ \hline \bf Zifencei & \bf 2.0 & \bf Ratification \\ + \bf Zicsr & \bf 2.0 & \bf Ratification \\ \bf M & \bf 2.0 & \bf Ratification \\ \bf A & \bf 2.0 & \bf Ratification \\ \bf F & \bf 2.2 & \bf Ratification \\ @@ -81,7 +82,7 @@ The major changes in this version of the document include: classic privileged architecture. Also, now allow access exceptions to be reported for misaligned access that should not be emulated. \item Moved FENCE.I out of the mandatory base and into a separate extension, - with Zifencei ISA name. FENCE.I was removed from the Linux ABI and is + with Zifencei ISA name. FENCE.I was removed from the Linux user ABI and is problematic in implementations with large incoherent instruction and data caches. However, it remains the only standard instruction-fetch coherence mechanism. @@ -91,8 +92,8 @@ The major changes in this version of the document include: produce illegal instruction exceptions in RV32E and RV64I chapters. \item Counter/timer instructions are now not considered part of the mandatory base ISA, and so CSR instructions were moved into separate - chapter, with the unprivileged counters moved into another separate - chapter. + chapter and marked as version 2.0, with the unprivileged counters + moved into another separate chapter. \item Explicitly defined the 16-bit half-precision floating-point format for floating-point instructions in the 2-bit {\em fmt field.} \item Defined the signed-zero behavior of FMIN.{\em fmt} and FMAX.{\em fmt}, |