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authorDaniel Lustig <dlustig@nvidia.com>2021-07-21 08:44:28 -0400
committerDaniel Lustig <dlustig@nvidia.com>2021-07-21 08:47:31 -0400
commitd8b50cdf69cdc6f84a96da3bbc438c1b347db743 (patch)
tree3567bc8fdb5d31a4c4a071cb04811ab7f3d73b44
parentbd32bde04b1f78810c2c50d32046a8542f022bc1 (diff)
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Clarify that N remains reserved under Sv39/48/57
Svnapot overrides that.
-rw-r--r--src/supervisor.tex13
1 files changed, 5 insertions, 8 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex
index f718ecc..e426beb 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -1812,13 +1812,10 @@ root page table is stored in the {\tt satp} register's PPN field.
The PTE format for Sv39 is shown in Figure~\ref{sv39pte}. Bits 9--0
have the same meaning as for Sv32.
-The N bit indicates that the page represents a
-naturally-aligned power-of-two range of contiguous translations, as defined in
-the Svnapot extension in Chapter~\ref{svnapot}.
-
-Bits 62--54 are reserved
-for future standard use and must be zeroed by software for forward compatibility.
-If any of these bits are set, a page-fault exception is raised.
+Bit 63 is reserved for use by the Svnapot extension in
+Chapter~\ref{svnapot}. Bits 62--54 are reserved for future standard use. All
+of these bits must be zeroed by software for forward compatibility. If any of
+these bits are set, a page-fault exception is raised.
\begin{commentary}
We reserved several PTE bits for a possible extension that improves
@@ -2124,7 +2121,7 @@ equals 8.
\chapter{``Svnapot'' Standard Extension for NAPOT Translation Contiguity, Version 0.1}
\label{svnapot}
-In Sv39, Sv48, and Sv57, when a PTE has N=1, the PTE represents a
+In Sv39, Sv48, and Sv57, when Svnapot is enabled and a PTE has N=1, the PTE represents a
translation that is part of a range of contiguous virtual-to-physical
translations with the same values for PTE bits 5--0. Such ranges must be of a
naturally aligned power-of-2 (NAPOT) granularity larger than the base page