diff options
| author | Bartek Gąsiorzewski <3065072+bgasiorzewski@users.noreply.github.com> | 2021-02-10 21:38:21 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-10 13:38:21 -0800 |
| commit | d506127c78abac9edfb6adb18990df67d49712d9 (patch) | |
| tree | e648e1d7cdf64bbab2ba996a15aaebf44a4e00ab | |
| parent | c4d3db2bb466921055c75f9ad4ea6d35963a42e5 (diff) | |
| download | riscv-isa-manual-d506127c78abac9edfb6adb18990df67d49712d9.zip riscv-isa-manual-d506127c78abac9edfb6adb18990df67d49712d9.tar.gz riscv-isa-manual-d506127c78abac9edfb6adb18990df67d49712d9.tar.bz2 | |
Clarify type of timer interrupt (#617)
Clarify that mtime >= mtimecmp results in a *machine* timer interrupt
being posted.
Co-authored-by: Bartosz Gasiorzewski <bartosz.gasiorzewski@imgtec.com>
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index 52739f8..666700e 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2238,7 +2238,7 @@ mechanism for determining the timebase of {\tt mtime}. The {\tt The {\tt mtime} register has a 64-bit precision on all RV32 and RV64 systems. Platforms provide a 64-bit memory-mapped machine-mode timer compare register ({\tt mtimecmp}). -A timer interrupt becomes pending whenever {\tt mtime} contains +A machine timer interrupt becomes pending whenever {\tt mtime} contains a value greater than or equal to {\tt mtimecmp}, treating the values as unsigned integers. The interrupt remains posted until {\tt mtimecmp} becomes greater than |