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| author | Andrew Waterman <andrew@sifive.com> | 2021-01-13 15:52:01 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-01-13 15:52:01 -0800 |
| commit | c50f27ed34f3147fb0e3a7bc903ccd64ac02502f (patch) | |
| tree | 4245390cc38caab8468b30a6436c88c33dc2fc0f | |
| parent | 8911fc383e1915811ed8be8530f24f8e52b13164 (diff) | |
| download | riscv-isa-manual-c50f27ed34f3147fb0e3a7bc903ccd64ac02502f.zip riscv-isa-manual-c50f27ed34f3147fb0e3a7bc903ccd64ac02502f.tar.gz riscv-isa-manual-c50f27ed34f3147fb0e3a7bc903ccd64ac02502f.tar.bz2 | |
should -> shall in definition of 0 instruction
| -rw-r--r-- | src/c.tex | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -1114,7 +1114,7 @@ illegal instruction. \begin{commentary} We reserve all-zero instructions to be illegal instructions to help trap attempts to execute zero-ed or non-existent portions of the -memory space. The all-zero value should not be redefined in any +memory space. The all-zero value shall not be redefined in any non-standard extension. Similarly, we reserve instructions with all bits set to 1 (corresponding to very long instructions in the RISC-V variable-length encoding scheme) as illegal to capture another common |