Fix typo, and remove page/access fault explanation

The explanation isn't really something that belongs in the Svnapot
chapter anyway.

Closes #4 and #5.

Thanks to @jhauser-us

1 files changed, 1 insertions, 6 deletions

diff --git a/src/supervisor.tex b/src/supervisor.tex
index 545edfd..9187e7a 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -2203,7 +2203,7 @@ algorithm in Section~\ref{sv32algorithm}, except that:
     replaced by $vpn[i][pte.napot\_bits-1:0]$.  If the encoding in $pte$ is
     {\em reserved} according to Table~\ref{ptenapot}, then a page-fault
     exception must be raised.
-  \item Implicit reads of NAPOT page table may create address-translation cache
+  \item Implicit reads of NAPOT page table entries may create address-translation cache
     entries mapping $a + va.vpn[j] \times \textrm{PTESIZE}$ to a copy of $pte$
     in which $pte.ppn[pte.napot\_bits-1:0]$ is replaced by
     $vpn[0][pte.napot\_bits-1:0]$, for any or all $j$ such that
@@ -2252,9 +2252,4 @@ algorithm in Section~\ref{sv32algorithm}, except that:
 
   Just as with normal PTEs, TLBs are permitted to cache NAPOT PTEs whose V
   (Valid) bit is clear.
-
-  Invalid NAPOT encodings were chosen to raise page-fault exceptions rather
-  than access-fault exceptions, following the convention that invalid PTE
-  configurations result in page-faults exceptions, while invalid access
-  types or accesses to invalid physical memory regions trigger page faults.
 \end{commentary}