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| author | Daniel Lustig <dlustig@nvidia.com> | 2021-07-15 07:38:50 -0400 |
|---|---|---|
| committer | Daniel Lustig <dlustig@nvidia.com> | 2021-07-15 07:38:50 -0400 |
| commit | bd32bde04b1f78810c2c50d32046a8542f022bc1 (patch) | |
| tree | 82d0f3570f350f89e824158237a0a62b85af543d | |
| parent | f41a5702d6437c032d88039a9c30b1b3022aff69 (diff) | |
| parent | 42bd6ecc07f48b424dc46851b70e6cc5f3140ff2 (diff) | |
| download | riscv-isa-manual-bd32bde04b1f78810c2c50d32046a8542f022bc1.zip riscv-isa-manual-bd32bde04b1f78810c2c50d32046a8542f022bc1.tar.gz riscv-isa-manual-bd32bde04b1f78810c2c50d32046a8542f022bc1.tar.bz2 | |
Merge branch 'virtual-memory' into Svnapot
| -rw-r--r-- | src/supervisor.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 876b79f..f718ecc 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -1024,8 +1024,8 @@ these data structures; however, these implicit references are ordinarily not ordered with respect to explicit loads and stores. Executing an SFENCE.VMA instruction guarantees that any previous stores already visible to the current RISC-V hart are ordered before certain implicit references by -subsequent instructions in that hart to the memory-management data structures, -and vice versa. The specific set of operations ordered by SFENCE.VMA is +subsequent instructions in that hart to the memory-management data structures. +The specific set of operations ordered by SFENCE.VMA is determined by {\em rs1} and {\em rs2}, as described below. SFENCE.VMA is also used to invalidate entries in the address-translation cache associated with a hart (see |