diff options
author | Daniel Lustig <dlustig@nvidia.com> | 2021-03-03 09:22:13 -0500 |
---|---|---|
committer | Daniel Lustig <dlustig@nvidia.com> | 2021-03-03 09:22:13 -0500 |
commit | a7bc9d2ae2013fd863dc285a2cbb8fd0ca935de9 (patch) | |
tree | 143311922a260859220004cc6c4dea738910bdcc | |
parent | 87f2ebad822f0d0828583b2a9a7e05e61008e1a0 (diff) | |
download | riscv-isa-manual-a7bc9d2ae2013fd863dc285a2cbb8fd0ca935de9.zip riscv-isa-manual-a7bc9d2ae2013fd863dc285a2cbb8fd0ca935de9.tar.gz riscv-isa-manual-a7bc9d2ae2013fd863dc285a2cbb8fd0ca935de9.tar.bz2 |
Fix formatting of preface bullet
-rw-r--r-- | src/priv-preface.tex | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/priv-preface.tex b/src/priv-preface.tex index 3e2435a..e3511fa 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -43,9 +43,9 @@ portability problems in practice: page-based virtual memory. \item PMP changes require an SFENCE.VMA on any hart that implements page-based virtual memory, even if VM is not currently enabled. -\item Allowed for speculative updates of page table entry A bits +\item Allowed for speculative updates of page table entry A bits. \item Clarify that PTEs with reserved bits set should trigger page-fault - exceptions + exceptions. \end{itemize} Additionally, the following compatible changes have been made since version @@ -63,12 +63,12 @@ Additionally, the following compatible changes have been made since version and access-fault exceptions. \item PMP reset values are now platform-defined. \item An additional 48 optional PMP registers have been defined. -\item Added the C bit to Sv39 and Sv48 PTEs to indicate custom encodings +\item Added the C bit to Sv39 and Sv48 PTEs to indicate custom encodings. \item Described the behavior of address-translation caches a little more - explicitly + explicitly. \item Slightly relaxed the atomicity requirement for A and D bit updates - performed by the implementation -\item Added Sv57 and Sv57x4 address translation modes + performed by the implementation. +\item Added Sv57 and Sv57x4 address translation modes. \end{itemize} Finally, the hypervisor architecture proposal has been extensively revised. |