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| author | Daniel Lustig <dlustig@nvidia.com> | 2021-05-17 08:24:51 -0400 |
|---|---|---|
| committer | Daniel Lustig <dlustig@nvidia.com> | 2021-05-17 10:39:50 -0400 |
| commit | 718054f0d6ec061fa97e2c104d51f7c79deef7ee (patch) | |
| tree | 92c6b5813ff06b11bf7829092cbb5a487396195f | |
| parent | 9c0f11d2a40ed19dac25b0991d2c70b3c843b2f1 (diff) | |
| download | riscv-isa-manual-718054f0d6ec061fa97e2c104d51f7c79deef7ee.zip riscv-isa-manual-718054f0d6ec061fa97e2c104d51f7c79deef7ee.tar.gz riscv-isa-manual-718054f0d6ec061fa97e2c104d51f7c79deef7ee.tar.bz2 | |
Fix typo
h/t @David-Horner
| -rw-r--r-- | src/supervisor.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 5ab7c3a..bca7bba 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -1284,7 +1284,7 @@ to the number of physical address bits found in the implementation. \begin{commentary} For example, consider an RV32 system supporting 34 bits of physical -address. When the value of {\tt satp}.MODE us Sv32, a 34-bit physical +address. When the value of {\tt satp}.MODE is Sv32, a 34-bit physical address is produced directly, and therefore no zero-extension is needed. When the value of {\tt satp}.MODE is Bare, the 32-bit virtual address is translated (unmodified) into a 32-bit physical address, and then that |