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authorDaniel Lustig <dlustig@nvidia.com>2021-08-06 08:36:38 -0400
committerDaniel Lustig <dlustig@nvidia.com>2021-08-06 08:36:38 -0400
commit5b8092807aa69abfd764b2443749c893d8470f6a (patch)
treead2ebc5853f252b620c25aa32df0305862d1decf
parent7a81fd2c6582c4685a4c9c9c2a49d8ffc19e3d42 (diff)
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Clarify Svpbmt non-leaf PTEs and other wording
Thanks to @scottj97 for pointing out the unclear wording.
-rw-r--r--src/supervisor.tex20
1 files changed, 13 insertions, 7 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex
index 18732fb..60d6122 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -2280,7 +2280,7 @@ algorithm in Section~\ref{sv32algorithm}, except that:
{\bf Warning! This draft specification is likely to change before being
accepted as standard by the RISC-V Foundation.}
-In Sv39, Sv48, and Sv57, bits 62--61 of the page table entry indicate the use
+In Sv39, Sv48, and Sv57, bits 62--61 of a leaf page table entry indicate the use
of page-based memory types that override the PMA(s) for the associated memory
pages. The encoding for the PBMT bits is captured in Table~\ref{pbmt}.
@@ -2307,6 +2307,9 @@ Future extensions may provide more and/or finer-grained control over which PMAs
can be overridden.
\end{commentary}
+For non-leaf PTEs, bits 62--61 are reserved for future standard use and must be
+cleared by software for forward compatibility.
+
If the underlying physical memory attribute for a page is I/O, then accesses to
that page with PBMT=1 will obey RVWMO or RVTSO rather than I/O strong ordering
rules, and accesses to such pages are considered main memory rather than I/O
@@ -2361,9 +2364,12 @@ performed. Such optimizations will likely improve performance when applied
with adequate care.
\end{commentary}
-When two-level paging is enabled within the H extension, the page-based memory
-types are applied in two stages. First, the G-stage PTE PBMT bits (if enabled)
-are applied to the attributes in the PMA to produce an intermediate set of
-attributes. Second, the VS-stage PTE PBMT bits (if enabled) are applied to
-these intermediate attributes to produce the final set of attributes used by
-accesses to the page in question.
+When two-stage address translation is enabled within the H extension, the
+page-based memory types are also applied in two stages. First, if
+{\tt hgatp}.MODE is not equal to zero, the G-stage PTE PBMT bits are applied to
+the attributes in the PMA to produce an intermediate set of attributes.
+Otherwise, the PMAs serve as the intermediate attributes. Second, if
+{\tt vsatp}.MODE is not equal to zero, the VS-stage PTE PBMT bits are applied
+to the intermediate attributes to produce the final set of attributes used by
+accesses to the page in question. Otherwise, the intermediate attributes are
+used as the final set of attributes.