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| author | John Hauser <31252952+jhauser-us@users.noreply.github.com> | 2021-08-18 01:12:11 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-08-18 01:12:11 -0700 |
| commit | fcbcb958aa49515e6345b1c08b3165f1db7bab67 (patch) | |
| tree | d0c3fa6b90ff7412df53e5dc72258f3daa9e2245 | |
| parent | 7446cb34b2877aefd19847181090c8b030395b5c (diff) | |
| download | riscv-isa-manual-fcbcb958aa49515e6345b1c08b3165f1db7bab67.zip riscv-isa-manual-fcbcb958aa49515e6345b1c08b3165f1db7bab67.tar.gz riscv-isa-manual-fcbcb958aa49515e6345b1c08b3165f1db7bab67.tar.bz2 | |
Update H chapter table of synchronous exception priorities (#717)
| -rw-r--r-- | src/hypervisor.tex | 39 |
1 files changed, 19 insertions, 20 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index 97c8615..44edab3 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -2754,36 +2754,38 @@ Because TSR and TVM in {\tt mstatus} are intended to impact only S-mode \begin{center} \begin{tabular}{|l|r|l|} \hline - Priority & Exception Code & Description \\ + Priority & Exc.\@ Code & Description \\ \hline {\em Highest} & 3 & Instruction address breakpoint \\ \hline - & 12 & Instruction page fault \\ + & & During instruction address translation: \\ + & 12, 20, 1 & \quad First encountered page fault, + guest-page fault, or access fault \\ \hline - & 20 & Instruction guest-page fault \\ - \hline - & 1 & Instruction access fault \\ + & & With physical address for instruction: \\ + & 1 & \quad Instruction access fault \\ \hline & 2 & Illegal instruction \\ & 22 & Virtual instruction \\ & 0 & Instruction address misaligned \\ & 8, 9, 10, 11 & Environment call \\ & 3 & Environment break \\ - & 3 & Load/Store/AMO address breakpoint \\ + & 3 & Load/store/AMO address breakpoint \\ \hline - {\em Optionally, these may have} - & 6 & Store/AMO address misaligned \\ - {\em lowest priority instead.} - & 4 & Load address misaligned \\ + & & Optionally: \\ + & 4, 6 & \quad Load/store/AMO address misaligned \\ \hline - & 15 & Store/AMO page fault \\ - & 13 & Load page fault \\ + & & During address translation for an explicit + memory access: \\ + & 13, 15, 21, 23, 5, 7 & \quad First encountered page fault, + guest-page fault, or access fault \\ \hline - & 23 & Store/AMO guest-page fault \\ - & 21 & Load guest-page fault \\ + & & With physical address for an explicit + memory access: \\ + & 5, 7 & \quad Load/store/AMO access fault \\ \hline - & 7 & Store/AMO access fault \\ - & 5 & Load access fault \\ + & & If not higher priority: \\ + {\em Lowest} & 4, 6 & \quad Load/store/AMO address misaligned \\ \hline \end{tabular} \end{center} @@ -2794,12 +2796,9 @@ implemented.% \label{tab:HSyncExcPrio} \end{table*} -If an instruction raises multiple synchronous exceptions, the +If an instruction may raise multiple synchronous exceptions, the decreasing priority order of Table~\ref{tab:HSyncExcPrio} indicates which exception is taken and reported in {\tt mcause} or {\tt scause}. -A virtual instruction exception has the same priority as an illegal -instruction exception, and a guest-page fault has lower priority than -a corresponding page fault. \FloatBarrier |