diff options
| author | Daniel Lustig <dlustig@nvidia.com> | 2021-09-09 19:51:05 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-09-09 16:51:05 -0700 |
| commit | 216aa2b9d084c04470e4a026e853ac9dd12a4d01 (patch) | |
| tree | fba48a5e553d820bdbb921eb557eaf96da7888e6 | |
| parent | 5a141642f7bf36ed0d2085de0ecc66ffbb41d909 (diff) | |
| download | riscv-isa-manual-216aa2b9d084c04470e4a026e853ac9dd12a4d01.zip riscv-isa-manual-216aa2b9d084c04470e4a026e853ac9dd12a4d01.tar.gz riscv-isa-manual-216aa2b9d084c04470e4a026e853ac9dd12a4d01.tar.bz2 | |
Fix a typo in Figure A.13. (#733)
Thanks to @YenHaoChen.
Closes #731
| -rw-r--r-- | src/memory.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/memory.tex b/src/memory.tex index 1af37ed..2cab253 100644 --- a/src/memory.tex +++ b/src/memory.tex @@ -668,7 +668,7 @@ Moreover, since SC is defined to carry dependencies from its source registers to { \tt\small \begin{tabular}{cl||cl} - \multicolumn{4}{c}{Initial values: 0(s0)=1; 0(s1)=1} \\ + \multicolumn{4}{c}{Initial values: 0(s0)=1; 0(s2)=1} \\ \\ \multicolumn{2}{c}{Hart 0} & \multicolumn{2}{c}{Hart 1} \\ \hline |