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authorBill Traynor <wmat@riscv.org>2023-03-30 14:09:49 -0400
committerBill Traynor <wmat@riscv.org>2023-03-30 14:09:49 -0400
commitb0671ec140c3a8136609b8e1befc5604030ff1b8 (patch)
tree984500a97b22506d3c6732091782b375dbe825f2
parentcc578b7b196cff613f465de87f452c4c4d61ebb3 (diff)
downloadriscv-isa-manual-b0671ec140c3a8136609b8e1befc5604030ff1b8.zip
riscv-isa-manual-b0671ec140c3a8136609b8e1befc5604030ff1b8.tar.gz
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Added privileged instructions diag
Implemented privileged instructions diagram as a bytefield-svg diagram.
-rw-r--r--src/hypervisor.adoc2
-rw-r--r--src/images/bytefield/priv-instr-set.edn236
-rw-r--r--src/machine.adoc4
-rw-r--r--src/priv-insns.adoc94
4 files changed, 237 insertions, 99 deletions
diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc
index 8ac250c..a68d436 100644
--- a/src/hypervisor.adoc
+++ b/src/hypervisor.adoc
@@ -1336,7 +1336,7 @@ shown in <<mtval2reg>>. When a trap is taken into
M-mode, `mtval2` is written with additional exception-specific
information, alongside `mtval`, to assist software in handling the trap.
-[[mtvalreg]]
+[[mtvalreg2]]
.Machine second trap value register (`mtval2`).
include::images/bytefield/mtval2reg.edn[]
diff --git a/src/images/bytefield/priv-instr-set.edn b/src/images/bytefield/priv-instr-set.edn
index c010b33..992a72f 100644
--- a/src/images/bytefield/priv-instr-set.edn
+++ b/src/images/bytefield/priv-instr-set.edn
@@ -28,6 +28,240 @@
(draw-box "funct3" {:span 3})
(draw-box "rd" {:span 4})
(draw-box "opcode" {:span 4})
-(draw-box "R-type" {:span 5 :text-anchor "start" :borders {}})
+(draw-box " R-type" {:span 5 :text-anchor "start" :borders {}})
+(draw-box "imm[11:0]" {:span 12})
+(draw-box "rs1" {:span 4})
+(draw-box "funct3" {:span 3})
+(draw-box "rd" {:span 4})
+(draw-box "opcode" {:span 4})
+(draw-box " I-type" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box nil {:span 32 :borders {}})
+(draw-box (text "Trap-Return Instructions" {:font-weight "bold" :font-size 24}) {:span 27 :borders {}})
+(draw-box nil {:span 5 :borders {}})
+
+(draw-box "0001000" {:span 8})
+(draw-box "00010" {:span 4})
+(draw-box "00000" {:span 4})
+(draw-box "000" {:span 3})
+(draw-box "00000" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box " SRET" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box "0011000" {:span 8})
+(draw-box "00010" {:span 4})
+(draw-box "00000" {:span 4})
+(draw-box "000" {:span 3})
+(draw-box "00000" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box " MRET" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box "0111000" {:span 8})
+(draw-box "00010" {:span 4})
+(draw-box "00000" {:span 4})
+(draw-box "000" {:span 3})
+(draw-box "00000" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box " MNRET" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box nil {:span 32 :borders {}})
+(draw-box (text "Interrupt-Management Instructions" {:font-weight "bold" :font-size 24}) {:span 27 :borders {}})
+(draw-box nil {:span 5 :borders {}})
+
+(draw-box "0001000" {:span 8})
+(draw-box "00101" {:span 4})
+(draw-box "00000" {:span 4})
+(draw-box "000" {:span 3})
+(draw-box "00000" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box "WFI" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box nil {:span 32 :borders {}})
+(draw-box (text "Supervisor Memory-Management Instructions" {:font-weight "bold" :font-size 24}) {:span 27 :borders {}})
+(draw-box nil {:span 5 :borders {}})
+
+(draw-box "0001001" {:span 8})
+(draw-box "rs2" {:span 4})
+(draw-box "rs1" {:span 4})
+(draw-box "000" {:span 3})
+(draw-box "00000" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box "SFENCE.VMA" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box nil {:span 32 :borders {}})
+(draw-box (text "Hypervisor Memory-Management Instructions" {:font-weight "bold" :font-size 24}) {:span 27 :borders {}})
+(draw-box nil {:span 5 :borders {}})
+
+(draw-box "0010001" {:span 8})
+(draw-box "rs2" {:span 4})
+(draw-box "rs1" {:span 4})
+(draw-box "000" {:span 3})
+(draw-box "00000" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box "HFENCE.VVMA" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box "0110001" {:span 8})
+(draw-box "rs2" {:span 4})
+(draw-box "rs1" {:span 4})
+(draw-box "000" {:span 3})
+(draw-box "00000" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box "HFENCE.GVMA" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box nil {:span 32 :borders {}})
+(draw-box (text "Hypervisor Virtual-Machine Load and Store Instructions" {:font-weight "bold" :font-size 24}) {:span 27 :borders {}})
+(draw-box nil {:span 5 :borders {}})
+
+(draw-box "0110001" {:span 8})
+(draw-box "00000" {:span 4})
+(draw-box "rs1" {:span 4})
+(draw-box "100" {:span 3})
+(draw-box "rd" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box "HLV.B" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box "0110001" {:span 8})
+(draw-box "00001" {:span 4})
+(draw-box "rs1" {:span 4})
+(draw-box "100" {:span 3})
+(draw-box "rd" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box "HLV.BU" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box "0110010" {:span 8})
+(draw-box "00000" {:span 4})
+(draw-box "rs1" {:span 4})
+(draw-box "100" {:span 3})
+(draw-box "rd" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box "HLV.H" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box "0110010" {:span 8})
+(draw-box "00001" {:span 4})
+(draw-box "rs1" {:span 4})
+(draw-box "100" {:span 3})
+(draw-box "rd" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box "HLV.HU" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box "0110100" {:span 8})
+(draw-box "00000" {:span 4})
+(draw-box "rs1" {:span 4})
+(draw-box "100" {:span 3})
+(draw-box "rd" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box "HLV.W" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box "0110010" {:span 8})
+(draw-box "00011" {:span 4})
+(draw-box "rs1" {:span 4})
+(draw-box "100" {:span 3})
+(draw-box "rd" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box "HLVX.HU" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box "0110010" {:span 8})
+(draw-box "00011" {:span 4})
+(draw-box "rs1" {:span 4})
+(draw-box "100" {:span 3})
+(draw-box "rd" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box "HLVX.WU" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box "0110001" {:span 8})
+(draw-box "rs2" {:span 4})
+(draw-box "rs1" {:span 4})
+(draw-box "100" {:span 3})
+(draw-box "00000" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box "HSV.B" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box "0110011" {:span 8})
+(draw-box "rs2" {:span 4})
+(draw-box "rs1" {:span 4})
+(draw-box "100" {:span 3})
+(draw-box "00000" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box "HSV.H" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box "0110101" {:span 8})
+(draw-box "rs2" {:span 4})
+(draw-box "rs1" {:span 4})
+(draw-box "100" {:span 3})
+(draw-box "00000" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box "HSV.W" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box nil {:span 32 :borders {}})
+(draw-box (text "Hypervisor Virtual-Machine Load and Store Instructions, RV64 only" {:font-weight "bold" :font-size 24}) {:span 27 :borders {}})
+(draw-box nil {:span 5 :borders {}})
+
+(draw-box "0110100" {:span 8})
+(draw-box "00001" {:span 4})
+(draw-box "rs1" {:span 4})
+(draw-box "100" {:span 3})
+(draw-box "rd" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box " HLV.WU" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box "0110110" {:span 8})
+(draw-box "00000" {:span 4})
+(draw-box "rs1" {:span 4})
+(draw-box "100" {:span 3})
+(draw-box "rd" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box " HLV.D" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box "0110111" {:span 8})
+(draw-box "rs2" {:span 4})
+(draw-box "rs1" {:span 4})
+(draw-box "100" {:span 3})
+(draw-box "00000" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box " HSV.D" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box nil {:span 32 :borders {}})
+(draw-box (text "Svinval Memory-Management Extension" {:font-weight "bold" :font-size 24}) {:span 27 :borders {}})
+(draw-box nil {:span 5 :borders {}})
+
+(draw-box "0001011" {:span 8})
+(draw-box "rs2" {:span 4})
+(draw-box "rs1" {:span 4})
+(draw-box "000" {:span 3})
+(draw-box "00000" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box " SINVAL.VMA" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box "0001100" {:span 8})
+(draw-box "00000" {:span 4})
+(draw-box "00000" {:span 4})
+(draw-box "000" {:span 3})
+(draw-box "00000" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box " SFENCE.W.INVAL" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box "0001100" {:span 8})
+(draw-box "00001" {:span 4})
+(draw-box "00000" {:span 4})
+(draw-box "000" {:span 3})
+(draw-box "00000" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box " SFENCE.INVAL.IR" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box "0010011" {:span 8})
+(draw-box "rs2" {:span 4})
+(draw-box "rs1" {:span 4})
+(draw-box "000" {:span 3})
+(draw-box "00000" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box " HINVAL.VVMA" {:span 5 :text-anchor "start" :borders {}})
+
+(draw-box "0110011" {:span 8})
+(draw-box "rs2" {:span 4})
+(draw-box "rs1" {:span 4})
+(draw-box "000" {:span 3})
+(draw-box "00000" {:span 4})
+(draw-box "1110011" {:span 4})
+(draw-box " HINVAL.GVMA" {:span 5 :text-anchor "start" :borders {}})
---- \ No newline at end of file
diff --git a/src/machine.adoc b/src/machine.adoc
index 0bc0d5c..d69f9be 100644
--- a/src/machine.adoc
+++ b/src/machine.adoc
@@ -1734,9 +1734,8 @@ MXLEN=64 as shown in [[menvcfg]], that controls
certain characteristics of the execution environment for modes less
privileged than M.
-[[menvcfg]]
.Machine environment configuration register (`menvcfg`) for MXLEN=64.
-include::images//bytefield/menvcfgreg.adoc[]
+include::images/bytefield/menvcfgreg.adoc[]
If bit FIOM (Fence of I/O implies Memory) is set to one in `menvcfg`,
FENCE instructions executed in modes less privileged than M are modified
@@ -2054,7 +2053,6 @@ The same "wait-for-event" template might be used for possible future
extensions that wait on memory locations changing, or message arrival.
====
-[[customsys]]
==== Custom SYSTEM Instructions
The subspace of the SYSTEM major opcode shown in <<customsys>> is designated for custom use. It is recommended that these instructions use bits 29:28 to designate the
diff --git a/src/priv-insns.adoc b/src/priv-insns.adoc
index d5c6e11..0020c2d 100644
--- a/src/priv-insns.adoc
+++ b/src/priv-insns.adoc
@@ -9,98 +9,4 @@ the ECALL and EBREAK instructions, are provided in Volume I of this
manual.
.RISC-V Privileged Instructions
-
include::images/bytefield/priv-instr-set.edn[]
-
-[cols="<,<,<,<,<,<,<,<,<,<,<,<",]
-|===
-| | | | | | | | | | | |
-
-| | | | | | | | | | | |
-
-| |funct7 | | | |rs2 | |rs1 |funct3 |rd |opcode |R-type
-
-| |imm[11:0] | | | | | |rs1 |funct3 |rd |opcode |I-type
-
-| | | | | | | | | | | |
-
-| |*Trap-Return Instructions* | | | | | | | | | |
-
-| |0001000 | | | |00010 | |00000 |000 |00000 |1110011 |SRET
-
-| |0011000 | | | |00010 | |00000 |000 |00000 |1110011 |MRET
-
-| |0111000 | | | |00010 | |00000 |000 |00000 |1110011 |MNRET
-
-| | | | | | | | | | | |
-
-| |*Interrupt-Management Instructions* | | | | | | | | | |
-
-| |0001000 | | | |00101 | |00000 |000 |00000 |1110011 |WFI
-
-| | | | | | | | | | | |
-
-| |*Supervisor Memory-Management Instructions* | | | | | | | | | |
-
-| |0001001 | | | |rs2 | |rs1 |000 |00000 |1110011 |SFENCE.VMA
-
-| | | | | | | | | | | |
-
-| |*Hypervisor Memory-Management Instructions* | | | | | | | | | |
-
-| |0010001 | | | |rs2 | |rs1 |000 |00000 |1110011 |HFENCE.VVMA
-
-| |0110001 | | | |rs2 | |rs1 |000 |00000 |1110011 |HFENCE.GVMA
-
-| | | | | | | | | | | |
-
-| |*Hypervisor Virtual-Machine Load and Store Instructions* | | | | | |
-| | | |
-
-| |0110000 | | | |00000 | |rs1 |100 |rd |1110011 |HLV.B
-
-| |0110000 | | | |00001 | |rs1 |100 |rd |1110011 |HLV.BU
-
-| |0110010 | | | |00000 | |rs1 |100 |rd |1110011 |HLV.H
-
-| |0110010 | | | |00001 | |rs1 |100 |rd |1110011 |HLV.HU
-
-| |0110100 | | | |00000 | |rs1 |100 |rd |1110011 |HLV.W
-
-| |0110010 | | | |00011 | |rs1 |100 |rd |1110011 |HLVX.HU
-
-| |0110100 | | | |00011 | |rs1 |100 |rd |1110011 |HLVX.WU
-
-| |0110001 | | | |rs2 | |rs1 |100 |00000 |1110011 |HSV.B
-
-| |0110011 | | | |rs2 | |rs1 |100 |00000 |1110011 |HSV.H
-
-| |0110101 | | | |rs2 | |rs1 |100 |00000 |1110011 |HSV.W
-
-| | | | | | | | | | | |
-
-| |*Hypervisor Virtual-Machine Load and Store Instructions, RV64 only* |
-| | | | | | | | |
-
-| |0110100 | | | |00001 | |rs1 |100 |rd |1110011 |HLV.WU
-
-| |0110110 | | | |00000 | |rs1 |100 |rd |1110011 |HLV.D
-
-| |0110111 | | | |rs2 | |rs1 |100 |00000 |1110011 |HSV.D
-
-| | | | | | | | | | | |
-
-| |*_Svinval_ Memory-Management Extension* | | | | | | | | | |
-
-| |0001011 | | | |rs2 | |rs1 |000 |00000 |1110011 |SINVAL.VMA
-
-| |0001100 | | | |00000 | |00000 |000 |00000 |1110011 |SFENCE.W.INVAL
-
-| |0001100 | | | |00001 | |00000 |000 |00000 |1110011 |SFENCE.INVAL.IR
-
-| |0010011 | | | |rs2 | |rs1 |000 |00000 |1110011 |HINVAL.VVMA
-
-| |0110011 | | | |rs2 | |rs1 |000 |00000 |1110011 |HINVAL.GVMA
-
-| | | | | | | | | | | |
-|===