From 5c613fe43d1bc44e6ae408b5356c7d60d93a1ca0 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 6 Jul 2016 03:24:33 -0700 Subject: Update to new PTE format --- encoding.h | 45 ++++++++++----------------------------------- v/vm.c | 20 +++++++++----------- 2 files changed, 19 insertions(+), 46 deletions(-) diff --git a/encoding.h b/encoding.h index e51ae43..641954a 100644 --- a/encoding.h +++ b/encoding.h @@ -18,6 +18,7 @@ #define MSTATUS_XS 0x00018000 #define MSTATUS_MPRV 0x00020000 #define MSTATUS_PUM 0x00040000 +#define MSTATUS_MXR 0x00080000 #define MSTATUS_VM 0x1F000000 #define MSTATUS32_SD 0x80000000 #define MSTATUS64_SD 0x8000000000000000 @@ -119,42 +120,18 @@ // page table entry (PTE) fields #define PTE_V 0x001 // Valid -#define PTE_TYPE 0x01E // Type -#define PTE_R 0x020 // Referenced -#define PTE_D 0x040 // Dirty -#define PTE_SOFT 0x380 // Reserved for Software - -#define PTE_TYPE_TABLE 0x00 -#define PTE_TYPE_TABLE_GLOBAL 0x02 -#define PTE_TYPE_URX_SR 0x04 -#define PTE_TYPE_URWX_SRW 0x06 -#define PTE_TYPE_UR_SR 0x08 -#define PTE_TYPE_URW_SRW 0x0A -#define PTE_TYPE_URX_SRX 0x0C -#define PTE_TYPE_URWX_SRWX 0x0E -#define PTE_TYPE_SR 0x10 -#define PTE_TYPE_SRW 0x12 -#define PTE_TYPE_SRX 0x14 -#define PTE_TYPE_SRWX 0x16 -#define PTE_TYPE_SR_GLOBAL 0x18 -#define PTE_TYPE_SRW_GLOBAL 0x1A -#define PTE_TYPE_SRX_GLOBAL 0x1C -#define PTE_TYPE_SRWX_GLOBAL 0x1E +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software #define PTE_PPN_SHIFT 10 -#define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1) -#define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1) -#define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1) -#define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1) -#define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1) -#define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1) -#define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1) - -#define PTE_CHECK_PERM(PTE, SUPERVISOR, STORE, FETCH) \ - ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \ - (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \ - ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE))) +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) #ifdef __riscv @@ -692,7 +669,6 @@ #define CSR_SBADADDR 0x143 #define CSR_SIP 0x144 #define CSR_SPTBR 0x180 -#define CSR_SASID 0x181 #define CSR_SCYCLE 0xd00 #define CSR_STIME 0xd01 #define CSR_SINSTRET 0xd02 @@ -1002,7 +978,6 @@ DECLARE_CSR(scause, CSR_SCAUSE) DECLARE_CSR(sbadaddr, CSR_SBADADDR) DECLARE_CSR(sip, CSR_SIP) DECLARE_CSR(sptbr, CSR_SPTBR) -DECLARE_CSR(sasid, CSR_SASID) DECLARE_CSR(scycle, CSR_SCYCLE) DECLARE_CSR(stime, CSR_STIME) DECLARE_CSR(sinstret, CSR_SINSTRET) diff --git a/v/vm.c b/v/vm.c index 2524363..545e85e 100644 --- a/v/vm.c +++ b/v/vm.c @@ -100,8 +100,8 @@ static void evict(unsigned long addr) freelist_t* node = &user_mapping[addr/PGSIZE]; if (node->addr) { - // check referenced and dirty bits - assert(user_l3pt[addr/PGSIZE] & PTE_R); + // check accessed and dirty bits + assert(user_l3pt[addr/PGSIZE] & PTE_A); if (memcmp((void*)addr, uva2kva(addr), PGSIZE)) { assert(user_l3pt[addr/PGSIZE] & PTE_D); memcpy((void*)addr, uva2kva(addr), PGSIZE); @@ -130,7 +130,7 @@ void handle_fault(unsigned long addr) if (freelist_head == freelist_tail) freelist_tail = 0; - user_l3pt[addr/PGSIZE] = (node->addr >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_URWX_SRW; + user_l3pt[addr/PGSIZE] = (node->addr >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X; asm volatile ("sfence.vm"); assert(user_mapping[addr/PGSIZE].addr == 0); @@ -151,8 +151,6 @@ void handle_trap(trapframe_t* tf) terminate(n); } - else if (tf->cause == CAUSE_FAULT_FETCH) - handle_fault(tf->epc); else if (tf->cause == CAUSE_ILLEGAL_INSTRUCTION) { assert(tf->epc % 4 == 0); @@ -166,7 +164,7 @@ void handle_trap(trapframe_t* tf) assert(!"illegal instruction"); tf->epc += 4; } - else if (tf->cause == CAUSE_FAULT_LOAD || tf->cause == CAUSE_FAULT_STORE) + else if (tf->cause == CAUSE_FAULT_FETCH || tf->cause == CAUSE_FAULT_LOAD || tf->cause == CAUSE_FAULT_STORE) handle_fault(tf->badvaddr); else assert(!"unexpected exception"); @@ -202,12 +200,12 @@ void vm_boot(long test_addr, long seed) #endif write_csr(sptbr, (uintptr_t)l1pt >> PGSHIFT); // map kernel to uppermost megapage - l1pt[PTES_PER_PT-1] = ((pte_t)kernel_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_TABLE; + l1pt[PTES_PER_PT-1] = ((pte_t)kernel_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; // map user to lowermost megapage - l1pt[0] = ((pte_t)user_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_TABLE; + l1pt[0] = ((pte_t)user_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; #ifdef __riscv64 - kernel_l2pt[PTES_PER_PT-1] = ((pte_t)kernel_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_TABLE; - user_l2pt[0] = ((pte_t)user_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_TABLE; + kernel_l2pt[PTES_PER_PT-1] = ((pte_t)kernel_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; + user_l2pt[0] = ((pte_t)user_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; #endif // set up supervisor trap handling @@ -232,7 +230,7 @@ void vm_boot(long test_addr, long seed) freelist_nodes[i].next = pa2kva(&freelist_nodes[i+1]); seed = LFSR_NEXT(seed); - kernel_l3pt[i] = ((i + DRAM_BASE/RISCV_PGSIZE) << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_SRWX; + kernel_l3pt[i] = ((i + DRAM_BASE/RISCV_PGSIZE) << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X; } freelist_nodes[MAX_TEST_PAGES-1].next = 0; -- cgit v1.1