From 4c356d46aace73c1562816a41e0f63948bdb0497 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 23 Sep 2018 21:11:53 -0700 Subject: Avoid writing reserved values to pmpaddr CSR --- p/riscv_test.h | 3 ++- v/vm.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/p/riscv_test.h b/p/riscv_test.h index 3fbcb50..7cb00d5 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -56,7 +56,8 @@ #define INIT_PMP \ la t0, 1f; \ csrw mtvec, t0; \ - li t0, -1; /* Set up a PMP to permit all accesses */ \ + /* Set up a PMP to permit all accesses */ \ + li t0, (1 << (31 + (__riscv_xlen / 64) * (53 - 31))) - 1; \ csrw pmpaddr0, t0; \ li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \ csrw pmpcfg0, t0; \ diff --git a/v/vm.c b/v/vm.c index a2e5533..d44bd8f 100644 --- a/v/vm.c +++ b/v/vm.c @@ -235,13 +235,14 @@ void vm_boot(uintptr_t test_addr) // Set up PMPs if present, ignoring illegal instruction trap if not. uintptr_t pmpc = PMP_NAPOT | PMP_R | PMP_W | PMP_X; + uintptr_t pmpa = ((uintptr_t)1 << (__riscv_xlen == 32 ? 31 : 53)) - 1; asm volatile ("la t0, 1f\n\t" "csrrw t0, mtvec, t0\n\t" "csrw pmpaddr0, %1\n\t" "csrw pmpcfg0, %0\n\t" ".align 2\n\t" "1:" - : : "r" (pmpc), "r" (-1UL) : "t0"); + : : "r" (pmpc), "r" (pmpa) : "t0"); // set up supervisor trap handling write_csr(stvec, pa2kva(trap_entry)); -- cgit v1.1