From 51671844c2588386ce3eacedf40d385e3c2b1484 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Wed, 22 Jun 2016 15:53:38 -0700 Subject: separate ua and um tests from ui tests --- isa/Makefile | 8 +++++ isa/rv32ua/Makefrag | 12 ++++++++ isa/rv32ua/amoadd_w.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv32ua/amoand_w.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv32ua/amomax_w.S | 49 +++++++++++++++++++++++++++++ isa/rv32ua/amomaxu_w.S | 49 +++++++++++++++++++++++++++++ isa/rv32ua/amomin_w.S | 49 +++++++++++++++++++++++++++++ isa/rv32ua/amominu_w.S | 49 +++++++++++++++++++++++++++++ isa/rv32ua/amoor_w.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv32ua/amoswap_w.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv32ua/amoxor_w.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv32ua/lrsc.S | 84 ++++++++++++++++++++++++++++++++++++++++++++++++++ isa/rv32ui/Makefrag | 5 --- isa/rv32ui/amoadd_w.S | 65 -------------------------------------- isa/rv32ui/amoand_w.S | 65 -------------------------------------- isa/rv32ui/amomax_w.S | 49 ----------------------------- isa/rv32ui/amomaxu_w.S | 49 ----------------------------- isa/rv32ui/amomin_w.S | 49 ----------------------------- isa/rv32ui/amominu_w.S | 49 ----------------------------- isa/rv32ui/amoor_w.S | 65 -------------------------------------- isa/rv32ui/amoswap_w.S | 65 -------------------------------------- isa/rv32ui/amoxor_w.S | 65 -------------------------------------- isa/rv32ui/div.S | 41 ------------------------ isa/rv32ui/divu.S | 41 ------------------------ isa/rv32ui/divuw.S | 41 ------------------------ isa/rv32ui/divw.S | 41 ------------------------ isa/rv32ui/lrsc.S | 84 -------------------------------------------------- isa/rv32ui/mul.S | 84 -------------------------------------------------- isa/rv32ui/mulh.S | 81 ------------------------------------------------ isa/rv32ui/mulhsu.S | 83 ------------------------------------------------- isa/rv32ui/mulhu.S | 82 ------------------------------------------------ isa/rv32ui/mulw.S | 72 ------------------------------------------- isa/rv32ui/rem.S | 41 ------------------------ isa/rv32ui/remu.S | 41 ------------------------ isa/rv32um/Makefrag | 13 ++++++++ isa/rv32um/div.S | 41 ++++++++++++++++++++++++ isa/rv32um/divu.S | 41 ++++++++++++++++++++++++ isa/rv32um/mul.S | 84 ++++++++++++++++++++++++++++++++++++++++++++++++++ isa/rv32um/mulh.S | 81 ++++++++++++++++++++++++++++++++++++++++++++++++ isa/rv32um/mulhsu.S | 83 +++++++++++++++++++++++++++++++++++++++++++++++++ isa/rv32um/mulhu.S | 82 ++++++++++++++++++++++++++++++++++++++++++++++++ isa/rv32um/rem.S | 41 ++++++++++++++++++++++++ isa/rv32um/remu.S | 41 ++++++++++++++++++++++++ isa/rv64ua/Makefrag | 13 ++++++++ isa/rv64ua/amoadd_d.S | 64 ++++++++++++++++++++++++++++++++++++++ isa/rv64ua/amoadd_w.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv64ua/amoand_d.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv64ua/amoand_w.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv64ua/amomax_d.S | 49 +++++++++++++++++++++++++++++ isa/rv64ua/amomax_w.S | 49 +++++++++++++++++++++++++++++ isa/rv64ua/amomaxu_d.S | 49 +++++++++++++++++++++++++++++ isa/rv64ua/amomaxu_w.S | 49 +++++++++++++++++++++++++++++ isa/rv64ua/amomin_d.S | 49 +++++++++++++++++++++++++++++ isa/rv64ua/amomin_w.S | 49 +++++++++++++++++++++++++++++ isa/rv64ua/amominu_d.S | 49 +++++++++++++++++++++++++++++ isa/rv64ua/amominu_w.S | 49 +++++++++++++++++++++++++++++ isa/rv64ua/amoor_d.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv64ua/amoor_w.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv64ua/amoswap_d.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv64ua/amoswap_w.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv64ua/amoxor_d.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv64ua/amoxor_w.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv64ua/lrsc.S | 84 ++++++++++++++++++++++++++++++++++++++++++++++++++ isa/rv64ui/Makefrag | 6 ---- isa/rv64ui/amoadd_d.S | 64 -------------------------------------- isa/rv64ui/amoadd_w.S | 65 -------------------------------------- isa/rv64ui/amoand_d.S | 65 -------------------------------------- isa/rv64ui/amoand_w.S | 65 -------------------------------------- isa/rv64ui/amomax_d.S | 49 ----------------------------- isa/rv64ui/amomax_w.S | 49 ----------------------------- isa/rv64ui/amomaxu_d.S | 49 ----------------------------- isa/rv64ui/amomaxu_w.S | 49 ----------------------------- isa/rv64ui/amomin_d.S | 49 ----------------------------- isa/rv64ui/amomin_w.S | 49 ----------------------------- isa/rv64ui/amominu_d.S | 49 ----------------------------- isa/rv64ui/amominu_w.S | 49 ----------------------------- isa/rv64ui/amoor_d.S | 65 -------------------------------------- isa/rv64ui/amoor_w.S | 65 -------------------------------------- isa/rv64ui/amoswap_d.S | 65 -------------------------------------- isa/rv64ui/amoswap_w.S | 65 -------------------------------------- isa/rv64ui/amoxor_d.S | 65 -------------------------------------- isa/rv64ui/amoxor_w.S | 65 -------------------------------------- isa/rv64ui/div.S | 41 ------------------------ isa/rv64ui/divu.S | 41 ------------------------ isa/rv64ui/divuw.S | 41 ------------------------ isa/rv64ui/divw.S | 41 ------------------------ isa/rv64ui/lrsc.S | 84 -------------------------------------------------- isa/rv64ui/mul.S | 78 ---------------------------------------------- isa/rv64ui/mulh.S | 72 ------------------------------------------- isa/rv64ui/mulhsu.S | 72 ------------------------------------------- isa/rv64ui/mulhu.S | 75 -------------------------------------------- isa/rv64ui/mulw.S | 72 ------------------------------------------- isa/rv64ui/rem.S | 41 ------------------------ isa/rv64ui/remu.S | 41 ------------------------ isa/rv64ui/remuw.S | 41 ------------------------ isa/rv64ui/remw.S | 42 ------------------------- isa/rv64um/Makefrag | 13 ++++++++ isa/rv64um/div.S | 41 ++++++++++++++++++++++++ isa/rv64um/divu.S | 41 ++++++++++++++++++++++++ isa/rv64um/divuw.S | 41 ++++++++++++++++++++++++ isa/rv64um/divw.S | 41 ++++++++++++++++++++++++ isa/rv64um/mul.S | 78 ++++++++++++++++++++++++++++++++++++++++++++++ isa/rv64um/mulh.S | 72 +++++++++++++++++++++++++++++++++++++++++++ isa/rv64um/mulhsu.S | 72 +++++++++++++++++++++++++++++++++++++++++++ isa/rv64um/mulhu.S | 75 ++++++++++++++++++++++++++++++++++++++++++++ isa/rv64um/mulw.S | 72 +++++++++++++++++++++++++++++++++++++++++++ isa/rv64um/rem.S | 41 ++++++++++++++++++++++++ isa/rv64um/remu.S | 41 ++++++++++++++++++++++++ isa/rv64um/remuw.S | 41 ++++++++++++++++++++++++ isa/rv64um/remw.S | 42 +++++++++++++++++++++++++ 110 files changed, 2981 insertions(+), 3087 deletions(-) create mode 100644 isa/rv32ua/Makefrag create mode 100644 isa/rv32ua/amoadd_w.S create mode 100644 isa/rv32ua/amoand_w.S create mode 100644 isa/rv32ua/amomax_w.S create mode 100644 isa/rv32ua/amomaxu_w.S create mode 100644 isa/rv32ua/amomin_w.S create mode 100644 isa/rv32ua/amominu_w.S create mode 100644 isa/rv32ua/amoor_w.S create mode 100644 isa/rv32ua/amoswap_w.S create mode 100644 isa/rv32ua/amoxor_w.S create mode 100644 isa/rv32ua/lrsc.S delete mode 100644 isa/rv32ui/amoadd_w.S delete mode 100644 isa/rv32ui/amoand_w.S delete mode 100644 isa/rv32ui/amomax_w.S delete mode 100644 isa/rv32ui/amomaxu_w.S delete mode 100644 isa/rv32ui/amomin_w.S delete mode 100644 isa/rv32ui/amominu_w.S delete mode 100644 isa/rv32ui/amoor_w.S delete mode 100644 isa/rv32ui/amoswap_w.S delete mode 100644 isa/rv32ui/amoxor_w.S delete mode 100644 isa/rv32ui/div.S delete mode 100644 isa/rv32ui/divu.S delete mode 100644 isa/rv32ui/divuw.S delete mode 100644 isa/rv32ui/divw.S delete mode 100644 isa/rv32ui/lrsc.S delete mode 100644 isa/rv32ui/mul.S delete mode 100644 isa/rv32ui/mulh.S delete mode 100644 isa/rv32ui/mulhsu.S delete mode 100644 isa/rv32ui/mulhu.S delete mode 100644 isa/rv32ui/mulw.S delete mode 100644 isa/rv32ui/rem.S delete mode 100644 isa/rv32ui/remu.S create mode 100644 isa/rv32um/Makefrag create mode 100644 isa/rv32um/div.S create mode 100644 isa/rv32um/divu.S create mode 100644 isa/rv32um/mul.S create mode 100644 isa/rv32um/mulh.S create mode 100644 isa/rv32um/mulhsu.S create mode 100644 isa/rv32um/mulhu.S create mode 100644 isa/rv32um/rem.S create mode 100644 isa/rv32um/remu.S create mode 100644 isa/rv64ua/Makefrag create mode 100644 isa/rv64ua/amoadd_d.S create mode 100644 isa/rv64ua/amoadd_w.S create mode 100644 isa/rv64ua/amoand_d.S create mode 100644 isa/rv64ua/amoand_w.S create mode 100644 isa/rv64ua/amomax_d.S create mode 100644 isa/rv64ua/amomax_w.S create mode 100644 isa/rv64ua/amomaxu_d.S create mode 100644 isa/rv64ua/amomaxu_w.S create mode 100644 isa/rv64ua/amomin_d.S create mode 100644 isa/rv64ua/amomin_w.S create mode 100644 isa/rv64ua/amominu_d.S create mode 100644 isa/rv64ua/amominu_w.S create mode 100644 isa/rv64ua/amoor_d.S create mode 100644 isa/rv64ua/amoor_w.S create mode 100644 isa/rv64ua/amoswap_d.S create mode 100644 isa/rv64ua/amoswap_w.S create mode 100644 isa/rv64ua/amoxor_d.S create mode 100644 isa/rv64ua/amoxor_w.S create mode 100644 isa/rv64ua/lrsc.S delete mode 100644 isa/rv64ui/amoadd_d.S delete mode 100644 isa/rv64ui/amoadd_w.S delete mode 100644 isa/rv64ui/amoand_d.S delete mode 100644 isa/rv64ui/amoand_w.S delete mode 100644 isa/rv64ui/amomax_d.S delete mode 100644 isa/rv64ui/amomax_w.S delete mode 100644 isa/rv64ui/amomaxu_d.S delete mode 100644 isa/rv64ui/amomaxu_w.S delete mode 100644 isa/rv64ui/amomin_d.S delete mode 100644 isa/rv64ui/amomin_w.S delete mode 100644 isa/rv64ui/amominu_d.S delete mode 100644 isa/rv64ui/amominu_w.S delete mode 100644 isa/rv64ui/amoor_d.S delete mode 100644 isa/rv64ui/amoor_w.S delete mode 100644 isa/rv64ui/amoswap_d.S delete mode 100644 isa/rv64ui/amoswap_w.S delete mode 100644 isa/rv64ui/amoxor_d.S delete mode 100644 isa/rv64ui/amoxor_w.S delete mode 100644 isa/rv64ui/div.S delete mode 100644 isa/rv64ui/divu.S delete mode 100644 isa/rv64ui/divuw.S delete mode 100644 isa/rv64ui/divw.S delete mode 100644 isa/rv64ui/lrsc.S delete mode 100644 isa/rv64ui/mul.S delete mode 100644 isa/rv64ui/mulh.S delete mode 100644 isa/rv64ui/mulhsu.S delete mode 100644 isa/rv64ui/mulhu.S delete mode 100644 isa/rv64ui/mulw.S delete mode 100644 isa/rv64ui/rem.S delete mode 100644 isa/rv64ui/remu.S delete mode 100644 isa/rv64ui/remuw.S delete mode 100644 isa/rv64ui/remw.S create mode 100644 isa/rv64um/Makefrag create mode 100644 isa/rv64um/div.S create mode 100644 isa/rv64um/divu.S create mode 100644 isa/rv64um/divuw.S create mode 100644 isa/rv64um/divw.S create mode 100644 isa/rv64um/mul.S create mode 100644 isa/rv64um/mulh.S create mode 100644 isa/rv64um/mulhsu.S create mode 100644 isa/rv64um/mulhu.S create mode 100644 isa/rv64um/mulw.S create mode 100644 isa/rv64um/rem.S create mode 100644 isa/rv64um/remu.S create mode 100644 isa/rv64um/remuw.S create mode 100644 isa/rv64um/remw.S diff --git a/isa/Makefile b/isa/Makefile index d07dfa6..4e1af6c 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -5,11 +5,15 @@ src_dir := . include $(src_dir)/rv64ui/Makefrag +include $(src_dir)/rv64um/Makefrag +include $(src_dir)/rv64ua/Makefrag include $(src_dir)/rv64uf/Makefrag include $(src_dir)/rv64ud/Makefrag include $(src_dir)/rv64si/Makefrag include $(src_dir)/rv64mi/Makefrag include $(src_dir)/rv32ui/Makefrag +include $(src_dir)/rv32um/Makefrag +include $(src_dir)/rv32ua/Makefrag include $(src_dir)/rv32si/Makefrag include $(src_dir)/rv32mi/Makefrag @@ -62,10 +66,14 @@ tests += $$($(1)_tests) endef $(eval $(call compile_template,rv32ui,-m32)) +$(eval $(call compile_template,rv32um,-m32)) +$(eval $(call compile_template,rv32ua,-m32)) $(eval $(call compile_template,rv32si,-m32)) $(eval $(call compile_template,rv32mi,-m32)) ifeq ($(XLEN),64) $(eval $(call compile_template,rv64ui)) +$(eval $(call compile_template,rv64um)) +$(eval $(call compile_template,rv64ua)) $(eval $(call compile_template,rv64uf)) $(eval $(call compile_template,rv64ud)) $(eval $(call compile_template,rv64si)) diff --git a/isa/rv32ua/Makefrag b/isa/rv32ua/Makefrag new file mode 100644 index 0000000..9af6c7e --- /dev/null +++ b/isa/rv32ua/Makefrag @@ -0,0 +1,12 @@ +#======================================================================= +# Makefrag for rv32ua tests +#----------------------------------------------------------------------- + +rv32ua_sc_tests = \ + amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ + lrsc \ + +rv32ua_p_tests = $(addprefix rv32ua-p-, $(rv32ua_sc_tests)) +rv32ua_v_tests = $(addprefix rv32ua-v-, $(rv32ua_sc_tests)) + +spike_tests += $(rv32ua_p_tests) $(rv32ua_v_tests) diff --git a/isa/rv32ua/amoadd_w.S b/isa/rv32ua/amoadd_w.S new file mode 100644 index 0000000..975ae1d --- /dev/null +++ b/isa/rv32ua/amoadd_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoadd_w.S +#----------------------------------------------------------------------------- +# +# Test amoadd.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoadd.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x7ffff800, \ + li a1, 0x80000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoadd.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffff800, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ua/amoand_w.S b/isa/rv32ua/amoand_w.S new file mode 100644 index 0000000..7c989c2 --- /dev/null +++ b/isa/rv32ua/amoand_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoand.w.S +#----------------------------------------------------------------------------- +# +# Test amoand.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoand.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x80000000, \ + li a1, 0x80000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoand.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ua/amomax_w.S b/isa/rv32ua/amomax_w.S new file mode 100644 index 0000000..698cf26 --- /dev/null +++ b/isa/rv32ua/amomax_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomax_d.S +#----------------------------------------------------------------------------- +# +# Test amomax.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 1; \ + sw x0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 1, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ua/amomaxu_w.S b/isa/rv32ua/amomaxu_w.S new file mode 100644 index 0000000..27c4ddf --- /dev/null +++ b/isa/rv32ua/amomaxu_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomaxu_d.S +#----------------------------------------------------------------------------- +# +# Test amomaxu.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffff; \ + sw x0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ua/amomin_w.S b/isa/rv32ua/amomin_w.S new file mode 100644 index 0000000..a6a0947 --- /dev/null +++ b/isa/rv32ua/amomin_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomin_d.S +#----------------------------------------------------------------------------- +# +# Test amomin.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffff; \ + sw x0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ua/amominu_w.S b/isa/rv32ua/amominu_w.S new file mode 100644 index 0000000..ce06e1c --- /dev/null +++ b/isa/rv32ua/amominu_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amominu_d.S +#----------------------------------------------------------------------------- +# +# Test amominu.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffff; \ + sw x0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ua/amoor_w.S b/isa/rv32ua/amoor_w.S new file mode 100644 index 0000000..0988c66 --- /dev/null +++ b/isa/rv32ua/amoor_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoor.w.S +#----------------------------------------------------------------------------- +# +# Test amoor.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffff800, \ + li a1, 1; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffff801, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ua/amoswap_w.S b/isa/rv32ua/amoswap_w.S new file mode 100644 index 0000000..a32ae74 --- /dev/null +++ b/isa/rv32ua/amoswap_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoswap_w.S +#----------------------------------------------------------------------------- +# +# Test amoswap.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoswap.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffff800, \ + li a1, 0x80000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoswap.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ua/amoxor_w.S b/isa/rv32ua/amoxor_w.S new file mode 100644 index 0000000..d4b775f --- /dev/null +++ b/isa/rv32ua/amoxor_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoxor_w.S +#----------------------------------------------------------------------------- +# +# Test amoxor.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoxor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x7ffff800, \ + li a1, 0xc0000001; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoxor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xbffff801, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ua/lrsc.S b/isa/rv32ua/lrsc.S new file mode 100644 index 0000000..3a3d05a --- /dev/null +++ b/isa/rv32ua/lrsc.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lrsr.S +#----------------------------------------------------------------------------- +# +# Test LR/SC instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + +# get a unique core id +la a0, coreid +li a1, 1 +amoadd.w a2, a1, (a0) + +# for now, only run this on core 0 +1:li a3, 1 +bgeu a2, a3, 1b + +1: lw a1, (a0) +bltu a1, a3, 1b + +# make sure that sc without a reservation fails. +TEST_CASE( 2, a4, 1, \ + la a0, foo; \ + sc.w a4, x0, (a0); \ +) + +# make sure that sc with the wrong reservation fails. +# TODO is this actually mandatory behavior? +TEST_CASE( 3, a4, 1, \ + la a0, foo; \ + add a1, a0, 1024; \ + lr.w a1, (a1); \ + sc.w a4, a1, (a0); \ +) + +# have each core add its coreid to foo 1000 times +la a0, foo +li a1, 1000 +1: lr.w a4, (a0) +add a4, a4, a2 +sc.w a4, a4, (a0) +bnez a4, 1b +add a1, a1, -1 +bnez a1, 1b + +# wait for all cores to finish +la a0, barrier +li a1, 1 +amoadd.w x0, a1, (a0) +1: lw a1, (a0) +blt a1, a3, 1b +fence + +# expected result is 1000*ncores*(ncores-1)/2 +TEST_CASE( 4, a2, 0, \ + la a0, foo; \ + li a1, 500; \ + mul a1, a1, a3; \ + add a2, a3, -1; \ + mul a1, a1, a2; \ + lw a2, (a0); \ + sub a2, a2, a1; \ +) + +TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +coreid: .word 0 +barrier: .word 0 +foo: .word 0 +RVTEST_DATA_END diff --git a/isa/rv32ui/Makefrag b/isa/rv32ui/Makefrag index 4bdebb5..6cb6c08 100644 --- a/isa/rv32ui/Makefrag +++ b/isa/rv32ui/Makefrag @@ -5,19 +5,14 @@ rv32ui_sc_tests = \ simple \ add addi \ - amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ - lrsc \ and andi \ auipc \ beq bge bgeu blt bltu bne \ - div divu \ fence_i \ j jal jalr \ lb lbu lh lhu lw \ lui \ - mul mulh mulhu mulhsu \ or ori \ - rem remu \ sb sh sw \ sll slli \ slt slti \ diff --git a/isa/rv32ui/amoadd_w.S b/isa/rv32ui/amoadd_w.S deleted file mode 100644 index 975ae1d..0000000 --- a/isa/rv32ui/amoadd_w.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoadd_w.S -#----------------------------------------------------------------------------- -# -# Test amoadd.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0x80000000, \ - li a0, 0x80000000; \ - li a1, 0xfffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoadd.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0x7ffff800, \ - li a1, 0x80000000; \ - li a4, 16384; \ - add a5, a3, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - amoadd.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xfffff800, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv32ui/amoand_w.S b/isa/rv32ui/amoand_w.S deleted file mode 100644 index 7c989c2..0000000 --- a/isa/rv32ui/amoand_w.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoand.w.S -#----------------------------------------------------------------------------- -# -# Test amoand.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0x80000000, \ - li a0, 0x80000000; \ - li a1, 0xfffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoand.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0x80000000, \ - li a1, 0x80000000; \ - li a4, 16384; \ - add a5, a3, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - amoand.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv32ui/amomax_w.S b/isa/rv32ui/amomax_w.S deleted file mode 100644 index 698cf26..0000000 --- a/isa/rv32ui/amomax_w.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomax_d.S -#----------------------------------------------------------------------------- -# -# Test amomax.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0x80000000, \ - li a0, 0x80000000; \ - li a1, 0xfffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - amomax.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 1; \ - sw x0, 0(a3); \ - amomax.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 1, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv32ui/amomaxu_w.S b/isa/rv32ui/amomaxu_w.S deleted file mode 100644 index 27c4ddf..0000000 --- a/isa/rv32ui/amomaxu_w.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomaxu_d.S -#----------------------------------------------------------------------------- -# -# Test amomaxu.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0x80000000, \ - li a0, 0x80000000; \ - li a1, 0xfffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - amomaxu.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 0xffffffff; \ - sw x0, 0(a3); \ - amomaxu.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv32ui/amomin_w.S b/isa/rv32ui/amomin_w.S deleted file mode 100644 index a6a0947..0000000 --- a/isa/rv32ui/amomin_w.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomin_d.S -#----------------------------------------------------------------------------- -# -# Test amomin.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0x80000000, \ - li a0, 0x80000000; \ - li a1, 0xfffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - amomin.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 0xffffffff; \ - sw x0, 0(a3); \ - amomin.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv32ui/amominu_w.S b/isa/rv32ui/amominu_w.S deleted file mode 100644 index ce06e1c..0000000 --- a/isa/rv32ui/amominu_w.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amominu_d.S -#----------------------------------------------------------------------------- -# -# Test amominu.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0x80000000, \ - li a0, 0x80000000; \ - li a1, 0xfffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - amominu.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 0xffffffff; \ - sw x0, 0(a3); \ - amominu.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv32ui/amoor_w.S b/isa/rv32ui/amoor_w.S deleted file mode 100644 index 0988c66..0000000 --- a/isa/rv32ui/amoor_w.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoor.w.S -#----------------------------------------------------------------------------- -# -# Test amoor.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0x80000000, \ - li a0, 0x80000000; \ - li a1, 0xfffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoor.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0xfffff800, \ - li a1, 1; \ - li a4, 16384; \ - add a5, a3, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - amoor.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xfffff801, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv32ui/amoswap_w.S b/isa/rv32ui/amoswap_w.S deleted file mode 100644 index a32ae74..0000000 --- a/isa/rv32ui/amoswap_w.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoswap_w.S -#----------------------------------------------------------------------------- -# -# Test amoswap.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0x80000000, \ - li a0, 0x80000000; \ - li a1, 0xfffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoswap.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0xfffff800, \ - li a1, 0x80000000; \ - li a4, 16384; \ - add a5, a3, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - amoswap.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv32ui/amoxor_w.S b/isa/rv32ui/amoxor_w.S deleted file mode 100644 index d4b775f..0000000 --- a/isa/rv32ui/amoxor_w.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoxor_w.S -#----------------------------------------------------------------------------- -# -# Test amoxor.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0x80000000, \ - li a0, 0x80000000; \ - li a1, 0xfffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoxor.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0x7ffff800, \ - li a1, 0xc0000001; \ - li a4, 16384; \ - add a5, a3, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - amoxor.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xbffff801, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv32ui/div.S b/isa/rv32ui/div.S deleted file mode 100644 index a4504a7..0000000 --- a/isa/rv32ui/div.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# div.S -#----------------------------------------------------------------------------- -# -# Test div instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, div, 3, 20, 6 ); - TEST_RR_OP( 3, div, -3, -20, 6 ); - TEST_RR_OP( 4, div, -3, 20, -6 ); - TEST_RR_OP( 5, div, 3, -20, -6 ); - - TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 ); - TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 ); - - TEST_RR_OP( 8, div, -1, -1<<63, 0 ); - TEST_RR_OP( 9, div, -1, 1, 0 ); - TEST_RR_OP(10, div, -1, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/divu.S b/isa/rv32ui/divu.S deleted file mode 100644 index cd348c9..0000000 --- a/isa/rv32ui/divu.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# divu.S -#----------------------------------------------------------------------------- -# -# Test divu instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, divu, 3, 20, 6 ); - TEST_RR_OP( 3, divu, 715827879, -20, 6 ); - TEST_RR_OP( 4, divu, 0, 20, -6 ); - TEST_RR_OP( 5, divu, 0, -20, -6 ); - - TEST_RR_OP( 6, divu, -1<<31, -1<<31, 1 ); - TEST_RR_OP( 7, divu, 0, -1<<31, -1 ); - - TEST_RR_OP( 8, divu, -1, -1<<31, 0 ); - TEST_RR_OP( 9, divu, -1, 1, 0 ); - TEST_RR_OP(10, divu, -1, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/divuw.S b/isa/rv32ui/divuw.S deleted file mode 100644 index 0868eeb..0000000 --- a/isa/rv32ui/divuw.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# divuw.S -#----------------------------------------------------------------------------- -# -# Test divuw instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, divuw, 3, 20, 6 ); - TEST_RR_OP( 3, divuw, 715827879, -20 << 32 >> 32, 6 ); - TEST_RR_OP( 4, divuw, 0, 20, -6 ); - TEST_RR_OP( 5, divuw, 0, -20, -6 ); - - TEST_RR_OP( 6, divuw, -1<<31, -1<<31, 1 ); - TEST_RR_OP( 7, divuw, 0, -1<<31, -1 ); - - TEST_RR_OP( 8, divuw, -1, -1<<31, 0 ); - TEST_RR_OP( 9, divuw, -1, 1, 0 ); - TEST_RR_OP(10, divuw, -1, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/divw.S b/isa/rv32ui/divw.S deleted file mode 100644 index 4d91749..0000000 --- a/isa/rv32ui/divw.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# divw.S -#----------------------------------------------------------------------------- -# -# Test divw instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, divw, 3, 20, 6 ); - TEST_RR_OP( 3, divw, -3, -20, 6 ); - TEST_RR_OP( 4, divw, -3, 20, -6 ); - TEST_RR_OP( 5, divw, 3, -20, -6 ); - - TEST_RR_OP( 6, divw, -1<<31, -1<<31, 1 ); - TEST_RR_OP( 7, divw, -1<<31, -1<<31, -1 ); - - TEST_RR_OP( 8, divw, -1, -1<<31, 0 ); - TEST_RR_OP( 9, divw, -1, 1, 0 ); - TEST_RR_OP(10, divw, -1, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/lrsc.S b/isa/rv32ui/lrsc.S deleted file mode 100644 index 3a3d05a..0000000 --- a/isa/rv32ui/lrsc.S +++ /dev/null @@ -1,84 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# lrsr.S -#----------------------------------------------------------------------------- -# -# Test LR/SC instructions. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - -# get a unique core id -la a0, coreid -li a1, 1 -amoadd.w a2, a1, (a0) - -# for now, only run this on core 0 -1:li a3, 1 -bgeu a2, a3, 1b - -1: lw a1, (a0) -bltu a1, a3, 1b - -# make sure that sc without a reservation fails. -TEST_CASE( 2, a4, 1, \ - la a0, foo; \ - sc.w a4, x0, (a0); \ -) - -# make sure that sc with the wrong reservation fails. -# TODO is this actually mandatory behavior? -TEST_CASE( 3, a4, 1, \ - la a0, foo; \ - add a1, a0, 1024; \ - lr.w a1, (a1); \ - sc.w a4, a1, (a0); \ -) - -# have each core add its coreid to foo 1000 times -la a0, foo -li a1, 1000 -1: lr.w a4, (a0) -add a4, a4, a2 -sc.w a4, a4, (a0) -bnez a4, 1b -add a1, a1, -1 -bnez a1, 1b - -# wait for all cores to finish -la a0, barrier -li a1, 1 -amoadd.w x0, a1, (a0) -1: lw a1, (a0) -blt a1, a3, 1b -fence - -# expected result is 1000*ncores*(ncores-1)/2 -TEST_CASE( 4, a2, 0, \ - la a0, foo; \ - li a1, 500; \ - mul a1, a1, a3; \ - add a2, a3, -1; \ - mul a1, a1, a2; \ - lw a2, (a0); \ - sub a2, a2, a1; \ -) - -TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -coreid: .word 0 -barrier: .word 0 -foo: .word 0 -RVTEST_DATA_END diff --git a/isa/rv32ui/mul.S b/isa/rv32ui/mul.S deleted file mode 100644 index 0368629..0000000 --- a/isa/rv32ui/mul.S +++ /dev/null @@ -1,84 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# mul.S -#----------------------------------------------------------------------------- -# -# Test mul instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP(32, mul, 0x00001200, 0x00007e00, 0xb6db6db7 ); - TEST_RR_OP(33, mul, 0x00001240, 0x00007fc0, 0xb6db6db7 ); - - TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, mul, 0x00000000, 0x00000000, 0xffff8000 ); - TEST_RR_OP( 6, mul, 0x00000000, 0x80000000, 0x00000000 ); - TEST_RR_OP( 7, mul, 0x00000000, 0x80000000, 0xffff8000 ); - - TEST_RR_OP(30, mul, 0x0000ff7f, 0xaaaaaaab, 0x0002fe7d ); - TEST_RR_OP(31, mul, 0x0000ff7f, 0x0002fe7d, 0xaaaaaaab ); - - TEST_RR_OP(34, mul, 0x00000000, 0xff000000, 0xff000000 ); - - TEST_RR_OP(35, mul, 0x00000001, 0xffffffff, 0xffffffff ); - TEST_RR_OP(36, mul, 0xffffffff, 0xffffffff, 0x00000001 ); - TEST_RR_OP(37, mul, 0xffffffff, 0x00000001, 0xffffffff ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 ); - TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 ); - TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 ); - TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 ); - TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 ); - - TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 ); - TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 ); - TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 ); - TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 ); - TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 ); - TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 ); - - TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 ); - TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 ); - TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 ); - TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 ); - TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 ); - TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 ); - - TEST_RR_ZEROSRC1( 26, mul, 0, 31 ); - TEST_RR_ZEROSRC2( 27, mul, 0, 32 ); - TEST_RR_ZEROSRC12( 28, mul, 0 ); - TEST_RR_ZERODEST( 29, mul, 33, 34 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/mulh.S b/isa/rv32ui/mulh.S deleted file mode 100644 index e583f5f..0000000 --- a/isa/rv32ui/mulh.S +++ /dev/null @@ -1,81 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# mulh.S -#----------------------------------------------------------------------------- -# -# Test mulh instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, mulh, 0x00000000, 0x00000000, 0xffff8000 ); - TEST_RR_OP( 6, mulh, 0x00000000, 0x80000000, 0x00000000 ); - TEST_RR_OP( 7, mulh, 0x00000000, 0x80000000, 0x00000000 ); - - TEST_RR_OP(30, mulh, 0xffff0081, 0xaaaaaaab, 0x0002fe7d ); - TEST_RR_OP(31, mulh, 0xffff0081, 0x0002fe7d, 0xaaaaaaab ); - - TEST_RR_OP(32, mulh, 0x00010000, 0xff000000, 0xff000000 ); - - TEST_RR_OP(33, mulh, 0x00000000, 0xffffffff, 0xffffffff ); - TEST_RR_OP(34, mulh, 0xffffffff, 0xffffffff, 0x00000001 ); - TEST_RR_OP(35, mulh, 0xffffffff, 0x00000001, 0xffffffff ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 8, mulh, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC2_EQ_DEST( 9, mulh, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC12_EQ_DEST( 10, mulh, 43264, 13<<20 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 11, 0, mulh, 36608, 13<<20, 11<<20 ); - TEST_RR_DEST_BYPASS( 12, 1, mulh, 39424, 14<<20, 11<<20 ); - TEST_RR_DEST_BYPASS( 13, 2, mulh, 42240, 15<<20, 11<<20 ); - - TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 42240, 15<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 42240, 15<<20, 11<<20 ); - - TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 42240, 15<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 42240, 15<<20, 11<<20 ); - - TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<26 ); - TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<26 ); - TEST_RR_ZEROSRC12( 28, mulh, 0 ); - TEST_RR_ZERODEST( 29, mulh, 33<<20, 34<<20 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/mulhsu.S b/isa/rv32ui/mulhsu.S deleted file mode 100644 index 28b3690..0000000 --- a/isa/rv32ui/mulhsu.S +++ /dev/null @@ -1,83 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# mulhsu.S -#----------------------------------------------------------------------------- -# -# Test mulhsu instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, mulhsu, 0x00000000, 0x00000000, 0xffff8000 ); - TEST_RR_OP( 6, mulhsu, 0x00000000, 0x80000000, 0x00000000 ); - TEST_RR_OP( 7, mulhsu, 0x80004000, 0x80000000, 0xffff8000 ); - - TEST_RR_OP(30, mulhsu, 0xffff0081, 0xaaaaaaab, 0x0002fe7d ); - TEST_RR_OP(31, mulhsu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab ); - - TEST_RR_OP(32, mulhsu, 0xff010000, 0xff000000, 0xff000000 ); - - TEST_RR_OP(33, mulhsu, 0xffffffff, 0xffffffff, 0xffffffff ); - TEST_RR_OP(34, mulhsu, 0xffffffff, 0xffffffff, 0x00000001 ); - TEST_RR_OP(35, mulhsu, 0x00000000, 0x00000001, 0xffffffff ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 43264, 13<<20 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 36608, 13<<20, 11<<20 ); - TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 39424, 14<<20, 11<<20 ); - TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 42240, 15<<20, 11<<20 ); - - TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 42240, 15<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 42240, 15<<20, 11<<20 ); - - TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 42240, 15<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 42240, 15<<20, 11<<20 ); - - TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<26 ); - TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<26 ); - TEST_RR_ZEROSRC12( 28, mulhsu, 0 ); - TEST_RR_ZERODEST( 29, mulhsu, 33<<20, 34<<20 ); - - - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/mulhu.S b/isa/rv32ui/mulhu.S deleted file mode 100644 index 601dcff..0000000 --- a/isa/rv32ui/mulhu.S +++ /dev/null @@ -1,82 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# mulhu.S -#----------------------------------------------------------------------------- -# -# Test mulhu instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, mulhu, 0x00000000, 0x00000000, 0xffff8000 ); - TEST_RR_OP( 6, mulhu, 0x00000000, 0x80000000, 0x00000000 ); - TEST_RR_OP( 7, mulhu, 0x7fffc000, 0x80000000, 0xffff8000 ); - - TEST_RR_OP(30, mulhu, 0x0001fefe, 0xaaaaaaab, 0x0002fe7d ); - TEST_RR_OP(31, mulhu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab ); - - TEST_RR_OP(32, mulhu, 0xfe010000, 0xff000000, 0xff000000 ); - - TEST_RR_OP(33, mulhu, 0xfffffffe, 0xffffffff, 0xffffffff ); - TEST_RR_OP(34, mulhu, 0x00000000, 0xffffffff, 0x00000001 ); - TEST_RR_OP(35, mulhu, 0x00000000, 0x00000001, 0xffffffff ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 8, mulhu, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC2_EQ_DEST( 9, mulhu, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC12_EQ_DEST( 10, mulhu, 43264, 13<<20 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 11, 0, mulhu, 36608, 13<<20, 11<<20 ); - TEST_RR_DEST_BYPASS( 12, 1, mulhu, 39424, 14<<20, 11<<20 ); - TEST_RR_DEST_BYPASS( 13, 2, mulhu, 42240, 15<<20, 11<<20 ); - - TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 42240, 15<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 42240, 15<<20, 11<<20 ); - - TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 42240, 15<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 42240, 15<<20, 11<<20 ); - - TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<26 ); - TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<26 ); - TEST_RR_ZEROSRC12( 28, mulhu, 0 ); - TEST_RR_ZERODEST( 29, mulhu, 33<<20, 34<<20 ); - - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/mulw.S b/isa/rv32ui/mulw.S deleted file mode 100644 index 577c93e..0000000 --- a/isa/rv32ui/mulw.S +++ /dev/null @@ -1,72 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# mulw.S -#----------------------------------------------------------------------------- -# -# Test mulw instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, mulw, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, mulw, 0x00000001, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, mulw, 0x00000015, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, mulw, 0x00000000, 0x00000000, 0xffff8000 ); - TEST_RR_OP( 6, mulw, 0x00000000, 0x80000000, 0x00000000 ); - TEST_RR_OP( 7, mulw, 0x00000000, 0x80000000, 0xffff8000 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 8, mulw, 143, 13, 11 ); - TEST_RR_SRC2_EQ_DEST( 9, mulw, 154, 14, 11 ); - TEST_RR_SRC12_EQ_DEST( 10, mulw, 169, 13 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 11, 0, mulw, 143, 13, 11 ); - TEST_RR_DEST_BYPASS( 12, 1, mulw, 154, 14, 11 ); - TEST_RR_DEST_BYPASS( 13, 2, mulw, 165, 15, 11 ); - - TEST_RR_SRC12_BYPASS( 14, 0, 0, mulw, 143, 13, 11 ); - TEST_RR_SRC12_BYPASS( 15, 0, 1, mulw, 154, 14, 11 ); - TEST_RR_SRC12_BYPASS( 16, 0, 2, mulw, 165, 15, 11 ); - TEST_RR_SRC12_BYPASS( 17, 1, 0, mulw, 143, 13, 11 ); - TEST_RR_SRC12_BYPASS( 18, 1, 1, mulw, 154, 14, 11 ); - TEST_RR_SRC12_BYPASS( 19, 2, 0, mulw, 165, 15, 11 ); - - TEST_RR_SRC21_BYPASS( 20, 0, 0, mulw, 143, 13, 11 ); - TEST_RR_SRC21_BYPASS( 21, 0, 1, mulw, 154, 14, 11 ); - TEST_RR_SRC21_BYPASS( 22, 0, 2, mulw, 165, 15, 11 ); - TEST_RR_SRC21_BYPASS( 23, 1, 0, mulw, 143, 13, 11 ); - TEST_RR_SRC21_BYPASS( 24, 1, 1, mulw, 154, 14, 11 ); - TEST_RR_SRC21_BYPASS( 25, 2, 0, mulw, 165, 15, 11 ); - - TEST_RR_ZEROSRC1( 26, mulw, 0, 31 ); - TEST_RR_ZEROSRC2( 27, mulw, 0, 32 ); - TEST_RR_ZEROSRC12( 28, mulw, 0 ); - TEST_RR_ZERODEST( 29, mulw, 33, 34 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/rem.S b/isa/rv32ui/rem.S deleted file mode 100644 index c318e2c..0000000 --- a/isa/rv32ui/rem.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# rem.S -#----------------------------------------------------------------------------- -# -# Test rem instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, rem, 2, 20, 6 ); - TEST_RR_OP( 3, rem, -2, -20, 6 ); - TEST_RR_OP( 4, rem, 2, 20, -6 ); - TEST_RR_OP( 5, rem, -2, -20, -6 ); - - TEST_RR_OP( 6, rem, 0, -1<<63, 1 ); - TEST_RR_OP( 7, rem, 0, -1<<63, -1 ); - - TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 ); - TEST_RR_OP( 9, rem, 1, 1, 0 ); - TEST_RR_OP(10, rem, 0, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/remu.S b/isa/rv32ui/remu.S deleted file mode 100644 index 38d641d..0000000 --- a/isa/rv32ui/remu.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# remu.S -#----------------------------------------------------------------------------- -# -# Test remu instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, remu, 2, 20, 6 ); - TEST_RR_OP( 3, remu, 2, -20, 6 ); - TEST_RR_OP( 4, remu, 20, 20, -6 ); - TEST_RR_OP( 5, remu, -20, -20, -6 ); - - TEST_RR_OP( 6, remu, 0, -1<<63, 1 ); - TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 ); - - TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 ); - TEST_RR_OP( 9, remu, 1, 1, 0 ); - TEST_RR_OP(10, remu, 0, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32um/Makefrag b/isa/rv32um/Makefrag new file mode 100644 index 0000000..50bffc8 --- /dev/null +++ b/isa/rv32um/Makefrag @@ -0,0 +1,13 @@ +#======================================================================= +# Makefrag for rv32um tests +#----------------------------------------------------------------------- + +rv32um_sc_tests = \ + div divu \ + mul mulh mulhsu mulhu \ + rem remu \ + +rv32um_p_tests = $(addprefix rv32um-p-, $(rv32um_sc_tests)) +rv32um_v_tests = $(addprefix rv32um-v-, $(rv32um_sc_tests)) + +spike_tests += $(rv32um_p_tests) $(rv32um_v_tests) diff --git a/isa/rv32um/div.S b/isa/rv32um/div.S new file mode 100644 index 0000000..a4504a7 --- /dev/null +++ b/isa/rv32um/div.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# div.S +#----------------------------------------------------------------------------- +# +# Test div instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, div, 3, 20, 6 ); + TEST_RR_OP( 3, div, -3, -20, 6 ); + TEST_RR_OP( 4, div, -3, 20, -6 ); + TEST_RR_OP( 5, div, 3, -20, -6 ); + + TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 ); + TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 ); + + TEST_RR_OP( 8, div, -1, -1<<63, 0 ); + TEST_RR_OP( 9, div, -1, 1, 0 ); + TEST_RR_OP(10, div, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32um/divu.S b/isa/rv32um/divu.S new file mode 100644 index 0000000..cd348c9 --- /dev/null +++ b/isa/rv32um/divu.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# divu.S +#----------------------------------------------------------------------------- +# +# Test divu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, divu, 3, 20, 6 ); + TEST_RR_OP( 3, divu, 715827879, -20, 6 ); + TEST_RR_OP( 4, divu, 0, 20, -6 ); + TEST_RR_OP( 5, divu, 0, -20, -6 ); + + TEST_RR_OP( 6, divu, -1<<31, -1<<31, 1 ); + TEST_RR_OP( 7, divu, 0, -1<<31, -1 ); + + TEST_RR_OP( 8, divu, -1, -1<<31, 0 ); + TEST_RR_OP( 9, divu, -1, 1, 0 ); + TEST_RR_OP(10, divu, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32um/mul.S b/isa/rv32um/mul.S new file mode 100644 index 0000000..0368629 --- /dev/null +++ b/isa/rv32um/mul.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mul.S +#----------------------------------------------------------------------------- +# +# Test mul instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, mul, 0x00001200, 0x00007e00, 0xb6db6db7 ); + TEST_RR_OP(33, mul, 0x00001240, 0x00007fc0, 0xb6db6db7 ); + + TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mul, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, mul, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, mul, 0x00000000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP(30, mul, 0x0000ff7f, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, mul, 0x0000ff7f, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(34, mul, 0x00000000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(35, mul, 0x00000001, 0xffffffff, 0xffffffff ); + TEST_RR_OP(36, mul, 0xffffffff, 0xffffffff, 0x00000001 ); + TEST_RR_OP(37, mul, 0xffffffff, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, mul, 0, 31 ); + TEST_RR_ZEROSRC2( 27, mul, 0, 32 ); + TEST_RR_ZEROSRC12( 28, mul, 0 ); + TEST_RR_ZERODEST( 29, mul, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32um/mulh.S b/isa/rv32um/mulh.S new file mode 100644 index 0000000..e583f5f --- /dev/null +++ b/isa/rv32um/mulh.S @@ -0,0 +1,81 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulh.S +#----------------------------------------------------------------------------- +# +# Test mulh instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulh, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, mulh, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, mulh, 0x00000000, 0x80000000, 0x00000000 ); + + TEST_RR_OP(30, mulh, 0xffff0081, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, mulh, 0xffff0081, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(32, mulh, 0x00010000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(33, mulh, 0x00000000, 0xffffffff, 0xffffffff ); + TEST_RR_OP(34, mulh, 0xffffffff, 0xffffffff, 0x00000001 ); + TEST_RR_OP(35, mulh, 0xffffffff, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulh, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC2_EQ_DEST( 9, mulh, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_EQ_DEST( 10, mulh, 43264, 13<<20 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulh, 36608, 13<<20, 11<<20 ); + TEST_RR_DEST_BYPASS( 12, 1, mulh, 39424, 14<<20, 11<<20 ); + TEST_RR_DEST_BYPASS( 13, 2, mulh, 42240, 15<<20, 11<<20 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 42240, 15<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 42240, 15<<20, 11<<20 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 42240, 15<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 42240, 15<<20, 11<<20 ); + + TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<26 ); + TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<26 ); + TEST_RR_ZEROSRC12( 28, mulh, 0 ); + TEST_RR_ZERODEST( 29, mulh, 33<<20, 34<<20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32um/mulhsu.S b/isa/rv32um/mulhsu.S new file mode 100644 index 0000000..28b3690 --- /dev/null +++ b/isa/rv32um/mulhsu.S @@ -0,0 +1,83 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulhsu.S +#----------------------------------------------------------------------------- +# +# Test mulhsu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulhsu, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, mulhsu, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, mulhsu, 0x80004000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP(30, mulhsu, 0xffff0081, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, mulhsu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(32, mulhsu, 0xff010000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(33, mulhsu, 0xffffffff, 0xffffffff, 0xffffffff ); + TEST_RR_OP(34, mulhsu, 0xffffffff, 0xffffffff, 0x00000001 ); + TEST_RR_OP(35, mulhsu, 0x00000000, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 43264, 13<<20 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 36608, 13<<20, 11<<20 ); + TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 39424, 14<<20, 11<<20 ); + TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 42240, 15<<20, 11<<20 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 42240, 15<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 42240, 15<<20, 11<<20 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 42240, 15<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 42240, 15<<20, 11<<20 ); + + TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<26 ); + TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<26 ); + TEST_RR_ZEROSRC12( 28, mulhsu, 0 ); + TEST_RR_ZERODEST( 29, mulhsu, 33<<20, 34<<20 ); + + + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32um/mulhu.S b/isa/rv32um/mulhu.S new file mode 100644 index 0000000..601dcff --- /dev/null +++ b/isa/rv32um/mulhu.S @@ -0,0 +1,82 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulhu.S +#----------------------------------------------------------------------------- +# +# Test mulhu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulhu, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, mulhu, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, mulhu, 0x7fffc000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP(30, mulhu, 0x0001fefe, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, mulhu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(32, mulhu, 0xfe010000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(33, mulhu, 0xfffffffe, 0xffffffff, 0xffffffff ); + TEST_RR_OP(34, mulhu, 0x00000000, 0xffffffff, 0x00000001 ); + TEST_RR_OP(35, mulhu, 0x00000000, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulhu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC2_EQ_DEST( 9, mulhu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_EQ_DEST( 10, mulhu, 43264, 13<<20 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulhu, 36608, 13<<20, 11<<20 ); + TEST_RR_DEST_BYPASS( 12, 1, mulhu, 39424, 14<<20, 11<<20 ); + TEST_RR_DEST_BYPASS( 13, 2, mulhu, 42240, 15<<20, 11<<20 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 42240, 15<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 42240, 15<<20, 11<<20 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 42240, 15<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 42240, 15<<20, 11<<20 ); + + TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<26 ); + TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<26 ); + TEST_RR_ZEROSRC12( 28, mulhu, 0 ); + TEST_RR_ZERODEST( 29, mulhu, 33<<20, 34<<20 ); + + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32um/rem.S b/isa/rv32um/rem.S new file mode 100644 index 0000000..c318e2c --- /dev/null +++ b/isa/rv32um/rem.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rem.S +#----------------------------------------------------------------------------- +# +# Test rem instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rem, 2, 20, 6 ); + TEST_RR_OP( 3, rem, -2, -20, 6 ); + TEST_RR_OP( 4, rem, 2, 20, -6 ); + TEST_RR_OP( 5, rem, -2, -20, -6 ); + + TEST_RR_OP( 6, rem, 0, -1<<63, 1 ); + TEST_RR_OP( 7, rem, 0, -1<<63, -1 ); + + TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 ); + TEST_RR_OP( 9, rem, 1, 1, 0 ); + TEST_RR_OP(10, rem, 0, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32um/remu.S b/isa/rv32um/remu.S new file mode 100644 index 0000000..38d641d --- /dev/null +++ b/isa/rv32um/remu.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# remu.S +#----------------------------------------------------------------------------- +# +# Test remu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, remu, 2, 20, 6 ); + TEST_RR_OP( 3, remu, 2, -20, 6 ); + TEST_RR_OP( 4, remu, 20, 20, -6 ); + TEST_RR_OP( 5, remu, -20, -20, -6 ); + + TEST_RR_OP( 6, remu, 0, -1<<63, 1 ); + TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 ); + + TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 ); + TEST_RR_OP( 9, remu, 1, 1, 0 ); + TEST_RR_OP(10, remu, 0, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64ua/Makefrag b/isa/rv64ua/Makefrag new file mode 100644 index 0000000..3af8856 --- /dev/null +++ b/isa/rv64ua/Makefrag @@ -0,0 +1,13 @@ +#======================================================================= +# Makefrag for rv64ua tests +#----------------------------------------------------------------------- + +rv64ua_sc_tests = \ + amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoxor_d amoswap_d \ + amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ + lrsc \ + +rv64ua_p_tests = $(addprefix rv64ua-p-, $(rv64ua_sc_tests)) +rv64ua_v_tests = $(addprefix rv64ua-v-, $(rv64ua_sc_tests)) + +spike_tests += $(rv64ua_p_tests) $(rv64ua_v_tests) diff --git a/isa/rv64ua/amoadd_d.S b/isa/rv64ua/amoadd_d.S new file mode 100644 index 0000000..c356bed --- /dev/null +++ b/isa/rv64ua/amoadd_d.S @@ -0,0 +1,64 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoadd_d.S +#----------------------------------------------------------------------------- +# +# Test amoadd.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoadd.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xffffffff7ffff800, \ + li a4, 16384; \ + add a5, a3, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + amoadd.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff7ffff000, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoadd_w.S b/isa/rv64ua/amoadd_w.S new file mode 100644 index 0000000..b3d1953 --- /dev/null +++ b/isa/rv64ua/amoadd_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoadd_w.S +#----------------------------------------------------------------------------- +# +# Test amoadd.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoadd.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x000000007ffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x000000007ffff800, \ + li a1, 0xffffffff80000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoadd.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoand_d.S b/isa/rv64ua/amoand_d.S new file mode 100644 index 0000000..13019ae --- /dev/null +++ b/isa/rv64ua/amoand_d.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoand_d.S +#----------------------------------------------------------------------------- +# +# Test amoand.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoand.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xffffffff80000000, \ + li a1, 0x0000000080000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + amoand.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoand_w.S b/isa/rv64ua/amoand_w.S new file mode 100644 index 0000000..a843888 --- /dev/null +++ b/isa/rv64ua/amoand_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoand.w.S +#----------------------------------------------------------------------------- +# +# Test amoand.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoand.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xffffffff80000000, \ + li a1, 0x0000000080000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoand.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amomax_d.S b/isa/rv64ua/amomax_d.S new file mode 100644 index 0000000..ea7e2d3 --- /dev/null +++ b/isa/rv64ua/amomax_d.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomax_d.S +#----------------------------------------------------------------------------- +# +# Test amomax.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amomax.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 1; \ + sd x0, 0(a3); \ + amomax.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 1, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amomax_w.S b/isa/rv64ua/amomax_w.S new file mode 100644 index 0000000..b3adbf0 --- /dev/null +++ b/isa/rv64ua/amomax_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomax_d.S +#----------------------------------------------------------------------------- +# +# Test amomax.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 1; \ + sw x0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 1, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amomaxu_d.S b/isa/rv64ua/amomaxu_d.S new file mode 100644 index 0000000..b340873 --- /dev/null +++ b/isa/rv64ua/amomaxu_d.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomaxu_d.S +#----------------------------------------------------------------------------- +# +# Test amomaxu.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amomaxu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sd x0, 0(a3); \ + amomaxu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amomaxu_w.S b/isa/rv64ua/amomaxu_w.S new file mode 100644 index 0000000..41346d1 --- /dev/null +++ b/isa/rv64ua/amomaxu_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomaxu_d.S +#----------------------------------------------------------------------------- +# +# Test amomaxu.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sw x0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amomin_d.S b/isa/rv64ua/amomin_d.S new file mode 100644 index 0000000..e6febbb --- /dev/null +++ b/isa/rv64ua/amomin_d.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomin_d.S +#----------------------------------------------------------------------------- +# +# Test amomin.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amomin.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sd x0, 0(a3); \ + amomin.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amomin_w.S b/isa/rv64ua/amomin_w.S new file mode 100644 index 0000000..96b547b --- /dev/null +++ b/isa/rv64ua/amomin_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomin_d.S +#----------------------------------------------------------------------------- +# +# Test amomin.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sw x0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amominu_d.S b/isa/rv64ua/amominu_d.S new file mode 100644 index 0000000..a1013f3 --- /dev/null +++ b/isa/rv64ua/amominu_d.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amominu_d.S +#----------------------------------------------------------------------------- +# +# Test amominu.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amominu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sd x0, 0(a3); \ + amominu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amominu_w.S b/isa/rv64ua/amominu_w.S new file mode 100644 index 0000000..0a9e265 --- /dev/null +++ b/isa/rv64ua/amominu_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amominu_d.S +#----------------------------------------------------------------------------- +# +# Test amominu.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sw x0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoor_d.S b/isa/rv64ua/amoor_d.S new file mode 100644 index 0000000..507e877 --- /dev/null +++ b/isa/rv64ua/amoor_d.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoor_d.S +#----------------------------------------------------------------------------- +# +# Test amoor.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 1; \ + li a4, 16384; \ + add a5, a3, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + amoor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffffffffffff801, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoor_w.S b/isa/rv64ua/amoor_w.S new file mode 100644 index 0000000..47978ba --- /dev/null +++ b/isa/rv64ua/amoor_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoor.w.S +#----------------------------------------------------------------------------- +# +# Test amoor.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 1; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffffffffffff801, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoswap_d.S b/isa/rv64ua/amoswap_d.S new file mode 100644 index 0000000..628f537 --- /dev/null +++ b/isa/rv64ua/amoswap_d.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoswap.d.S +#----------------------------------------------------------------------------- +# +# Test amoswap.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoswap.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 0x0000000080000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + amoswap.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoswap_w.S b/isa/rv64ua/amoswap_w.S new file mode 100644 index 0000000..c09b866 --- /dev/null +++ b/isa/rv64ua/amoswap_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoswap_w.S +#----------------------------------------------------------------------------- +# +# Test amoswap.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoswap.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 0x0000000080000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoswap.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoxor_d.S b/isa/rv64ua/amoxor_d.S new file mode 100644 index 0000000..f446121 --- /dev/null +++ b/isa/rv64ua/amoxor_d.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoxor_d.S +#----------------------------------------------------------------------------- +# +# Test amoxor.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoxor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x000000007ffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x000000007ffff800, \ + li a1, 1; \ + li a4, 16384; \ + add a5, a3, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + amoxor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x000000007ffff801, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoxor_w.S b/isa/rv64ua/amoxor_w.S new file mode 100644 index 0000000..2b92323 --- /dev/null +++ b/isa/rv64ua/amoxor_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoxor_w.S +#----------------------------------------------------------------------------- +# +# Test amoxor.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoxor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x000000007ffff800, \ + li a1, 0xc0000001; \ + li a4, 16384; \ + add a5, a3, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + amoxor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffbffff801, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/lrsc.S b/isa/rv64ua/lrsc.S new file mode 100644 index 0000000..9422739 --- /dev/null +++ b/isa/rv64ua/lrsc.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lrsr.S +#----------------------------------------------------------------------------- +# +# Test LR/SC instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + +# get a unique core id +la a0, coreid +li a1, 1 +amoadd.w a2, a1, (a0) + +# for now, only run this on core 0 +1:li a3, 1 +bgeu a2, a3, 1b + +1: lw a1, (a0) +bltu a1, a3, 1b + +# make sure that sc without a reservation fails. +TEST_CASE( 2, a4, 1, \ + la a0, foo; \ + sc.w a4, x0, (a0); \ +) + +# make sure that sc with the wrong reservation fails. +# TODO is this actually mandatory behavior? +TEST_CASE( 3, a4, 1, \ + la a0, foo; \ + add a1, a0, 1024; \ + lr.w a1, (a1); \ + sc.w a4, a1, (a0); \ +) + +# have each core add its coreid to foo 1000 times +la a0, foo +li a1, 1000 +1: lr.w a4, (a0) +add a4, a4, a2 +sc.w a4, a4, (a0) +bnez a4, 1b +add a1, a1, -1 +bnez a1, 1b + +# wait for all cores to finish +la a0, barrier +li a1, 1 +amoadd.w x0, a1, (a0) +1: lw a1, (a0) +blt a1, a3, 1b +fence + +# expected result is 1000*ncores*(ncores-1)/2 +TEST_CASE( 4, a2, 0, \ + la a0, foo; \ + li a1, 500; \ + mul a1, a1, a3; \ + add a2, a3, -1; \ + mul a1, a1, a2; \ + lw a2, (a0); \ + sub a2, a2, a1; \ +) + +TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +coreid: .word 0 +barrier: .word 0 +foo: .word 0 +RVTEST_DATA_END diff --git a/isa/rv64ui/Makefrag b/isa/rv64ui/Makefrag index 4af2504..7920b99 100644 --- a/isa/rv64ui/Makefrag +++ b/isa/rv64ui/Makefrag @@ -4,21 +4,15 @@ rv64ui_sc_tests = \ add addi addiw addw \ - amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoxor_d amoswap_d \ - amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ - lrsc \ and andi \ auipc \ beq bge bgeu blt bltu bne \ - div divu divuw divw \ example simple \ fence_i \ j jal jalr \ lb lbu lh lhu lw lwu ld \ lui \ - mul mulh mulhsu mulhu mulw \ or ori \ - rem remu remuw remw \ sb sh sw sd \ sll slli slliw sllw \ slt slti sltiu sltu \ diff --git a/isa/rv64ui/amoadd_d.S b/isa/rv64ui/amoadd_d.S deleted file mode 100644 index c356bed..0000000 --- a/isa/rv64ui/amoadd_d.S +++ /dev/null @@ -1,64 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoadd_d.S -#----------------------------------------------------------------------------- -# -# Test amoadd.d instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoadd.d a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0xffffffff7ffff800, \ - li a4, 16384; \ - add a5, a3, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - amoadd.d a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xffffffff7ffff000, ld a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amoadd_w.S b/isa/rv64ui/amoadd_w.S deleted file mode 100644 index b3d1953..0000000 --- a/isa/rv64ui/amoadd_w.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoadd_w.S -#----------------------------------------------------------------------------- -# -# Test amoadd.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoadd.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0x000000007ffff800, lw a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0x000000007ffff800, \ - li a1, 0xffffffff80000000; \ - li a4, 16384; \ - add a5, a3, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - amoadd.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xfffffffffffff800, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amoand_d.S b/isa/rv64ui/amoand_d.S deleted file mode 100644 index 13019ae..0000000 --- a/isa/rv64ui/amoand_d.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoand_d.S -#----------------------------------------------------------------------------- -# -# Test amoand.d instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoand.d a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0xffffffff80000000, \ - li a1, 0x0000000080000000; \ - li a4, 16384; \ - add a5, a3, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - amoand.d a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amoand_w.S b/isa/rv64ui/amoand_w.S deleted file mode 100644 index a843888..0000000 --- a/isa/rv64ui/amoand_w.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoand.w.S -#----------------------------------------------------------------------------- -# -# Test amoand.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoand.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0xffffffff80000000, \ - li a1, 0x0000000080000000; \ - li a4, 16384; \ - add a5, a3, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - amoand.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amomax_d.S b/isa/rv64ui/amomax_d.S deleted file mode 100644 index ea7e2d3..0000000 --- a/isa/rv64ui/amomax_d.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomax_d.S -#----------------------------------------------------------------------------- -# -# Test amomax.d instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - amomax.d a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 1; \ - sd x0, 0(a3); \ - amomax.d a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 1, ld a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amomax_w.S b/isa/rv64ui/amomax_w.S deleted file mode 100644 index b3adbf0..0000000 --- a/isa/rv64ui/amomax_w.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomax_d.S -#----------------------------------------------------------------------------- -# -# Test amomax.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - amomax.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 1; \ - sw x0, 0(a3); \ - amomax.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 1, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amomaxu_d.S b/isa/rv64ui/amomaxu_d.S deleted file mode 100644 index b340873..0000000 --- a/isa/rv64ui/amomaxu_d.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomaxu_d.S -#----------------------------------------------------------------------------- -# -# Test amomaxu.d instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - amomaxu.d a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 0xffffffffffffffff; \ - sd x0, 0(a3); \ - amomaxu.d a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amomaxu_w.S b/isa/rv64ui/amomaxu_w.S deleted file mode 100644 index 41346d1..0000000 --- a/isa/rv64ui/amomaxu_w.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomaxu_d.S -#----------------------------------------------------------------------------- -# -# Test amomaxu.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - amomaxu.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 0xffffffffffffffff; \ - sw x0, 0(a3); \ - amomaxu.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amomin_d.S b/isa/rv64ui/amomin_d.S deleted file mode 100644 index e6febbb..0000000 --- a/isa/rv64ui/amomin_d.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomin_d.S -#----------------------------------------------------------------------------- -# -# Test amomin.d instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - amomin.d a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 0xffffffffffffffff; \ - sd x0, 0(a3); \ - amomin.d a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amomin_w.S b/isa/rv64ui/amomin_w.S deleted file mode 100644 index 96b547b..0000000 --- a/isa/rv64ui/amomin_w.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomin_d.S -#----------------------------------------------------------------------------- -# -# Test amomin.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - amomin.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 0xffffffffffffffff; \ - sw x0, 0(a3); \ - amomin.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amominu_d.S b/isa/rv64ui/amominu_d.S deleted file mode 100644 index a1013f3..0000000 --- a/isa/rv64ui/amominu_d.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amominu_d.S -#----------------------------------------------------------------------------- -# -# Test amominu.d instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - amominu.d a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 0xffffffffffffffff; \ - sd x0, 0(a3); \ - amominu.d a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0, ld a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amominu_w.S b/isa/rv64ui/amominu_w.S deleted file mode 100644 index 0a9e265..0000000 --- a/isa/rv64ui/amominu_w.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amominu_d.S -#----------------------------------------------------------------------------- -# -# Test amominu.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - amominu.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 0xffffffffffffffff; \ - sw x0, 0(a3); \ - amominu.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amoor_d.S b/isa/rv64ui/amoor_d.S deleted file mode 100644 index 507e877..0000000 --- a/isa/rv64ui/amoor_d.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoor_d.S -#----------------------------------------------------------------------------- -# -# Test amoor.d instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoor.d a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0xfffffffffffff800, \ - li a1, 1; \ - li a4, 16384; \ - add a5, a3, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - amoor.d a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xfffffffffffff801, ld a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amoor_w.S b/isa/rv64ui/amoor_w.S deleted file mode 100644 index 47978ba..0000000 --- a/isa/rv64ui/amoor_w.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoor.w.S -#----------------------------------------------------------------------------- -# -# Test amoor.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoor.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0xfffffffffffff800, \ - li a1, 1; \ - li a4, 16384; \ - add a5, a3, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - amoor.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xfffffffffffff801, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amoswap_d.S b/isa/rv64ui/amoswap_d.S deleted file mode 100644 index 628f537..0000000 --- a/isa/rv64ui/amoswap_d.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoswap.d.S -#----------------------------------------------------------------------------- -# -# Test amoswap.d instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoswap.d a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0xfffffffffffff800, \ - li a1, 0x0000000080000000; \ - li a4, 16384; \ - add a5, a3, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - amoswap.d a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amoswap_w.S b/isa/rv64ui/amoswap_w.S deleted file mode 100644 index c09b866..0000000 --- a/isa/rv64ui/amoswap_w.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoswap_w.S -#----------------------------------------------------------------------------- -# -# Test amoswap.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoswap.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0xfffffffffffff800, \ - li a1, 0x0000000080000000; \ - li a4, 16384; \ - add a5, a3, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - amoswap.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amoxor_d.S b/isa/rv64ui/amoxor_d.S deleted file mode 100644 index f446121..0000000 --- a/isa/rv64ui/amoxor_d.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoxor_d.S -#----------------------------------------------------------------------------- -# -# Test amoxor.d instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoxor.d a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0x000000007ffff800, ld a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0x000000007ffff800, \ - li a1, 1; \ - li a4, 16384; \ - add a5, a3, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - amoxor.d a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0x000000007ffff801, ld a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amoxor_w.S b/isa/rv64ui/amoxor_w.S deleted file mode 100644 index 2b92323..0000000 --- a/isa/rv64ui/amoxor_w.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoxor_w.S -#----------------------------------------------------------------------------- -# -# Test amoxor.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoxor.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0x000000007ffff800, \ - li a1, 0xc0000001; \ - li a4, 16384; \ - add a5, a3, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - amoxor.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xffffffffbffff801, ld a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/div.S b/isa/rv64ui/div.S deleted file mode 100644 index ee21f0c..0000000 --- a/isa/rv64ui/div.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# div.S -#----------------------------------------------------------------------------- -# -# Test div instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, div, 3, 20, 6 ); - TEST_RR_OP( 3, div, -3, -20, 6 ); - TEST_RR_OP( 4, div, -3, 20, -6 ); - TEST_RR_OP( 5, div, 3, -20, -6 ); - - TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 ); - TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 ); - - TEST_RR_OP( 8, div, -1, -1<<63, 0 ); - TEST_RR_OP( 9, div, -1, 1, 0 ); - TEST_RR_OP(10, div, -1, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/divu.S b/isa/rv64ui/divu.S deleted file mode 100644 index e63fd65..0000000 --- a/isa/rv64ui/divu.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# divu.S -#----------------------------------------------------------------------------- -# -# Test divu instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, divu, 3, 20, 6 ); - TEST_RR_OP( 3, divu, 3074457345618258599, -20, 6 ); - TEST_RR_OP( 4, divu, 0, 20, -6 ); - TEST_RR_OP( 5, divu, 0, -20, -6 ); - - TEST_RR_OP( 6, divu, -1<<63, -1<<63, 1 ); - TEST_RR_OP( 7, divu, 0, -1<<63, -1 ); - - TEST_RR_OP( 8, divu, -1, -1<<63, 0 ); - TEST_RR_OP( 9, divu, -1, 1, 0 ); - TEST_RR_OP(10, divu, -1, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/divuw.S b/isa/rv64ui/divuw.S deleted file mode 100644 index 4c9eee7..0000000 --- a/isa/rv64ui/divuw.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# divuw.S -#----------------------------------------------------------------------------- -# -# Test divuw instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, divuw, 3, 20, 6 ); - TEST_RR_OP( 3, divuw, 715827879, -20 << 32 >> 32, 6 ); - TEST_RR_OP( 4, divuw, 0, 20, -6 ); - TEST_RR_OP( 5, divuw, 0, -20, -6 ); - - TEST_RR_OP( 6, divuw, -1<<31, -1<<31, 1 ); - TEST_RR_OP( 7, divuw, 0, -1<<31, -1 ); - - TEST_RR_OP( 8, divuw, -1, -1<<31, 0 ); - TEST_RR_OP( 9, divuw, -1, 1, 0 ); - TEST_RR_OP(10, divuw, -1, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/divw.S b/isa/rv64ui/divw.S deleted file mode 100644 index 4cffa1a..0000000 --- a/isa/rv64ui/divw.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# divw.S -#----------------------------------------------------------------------------- -# -# Test divw instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, divw, 3, 20, 6 ); - TEST_RR_OP( 3, divw, -3, -20, 6 ); - TEST_RR_OP( 4, divw, -3, 20, -6 ); - TEST_RR_OP( 5, divw, 3, -20, -6 ); - - TEST_RR_OP( 6, divw, -1<<31, -1<<31, 1 ); - TEST_RR_OP( 7, divw, -1<<31, -1<<31, -1 ); - - TEST_RR_OP( 8, divw, -1, -1<<31, 0 ); - TEST_RR_OP( 9, divw, -1, 1, 0 ); - TEST_RR_OP(10, divw, -1, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/lrsc.S b/isa/rv64ui/lrsc.S deleted file mode 100644 index 9422739..0000000 --- a/isa/rv64ui/lrsc.S +++ /dev/null @@ -1,84 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# lrsr.S -#----------------------------------------------------------------------------- -# -# Test LR/SC instructions. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - -# get a unique core id -la a0, coreid -li a1, 1 -amoadd.w a2, a1, (a0) - -# for now, only run this on core 0 -1:li a3, 1 -bgeu a2, a3, 1b - -1: lw a1, (a0) -bltu a1, a3, 1b - -# make sure that sc without a reservation fails. -TEST_CASE( 2, a4, 1, \ - la a0, foo; \ - sc.w a4, x0, (a0); \ -) - -# make sure that sc with the wrong reservation fails. -# TODO is this actually mandatory behavior? -TEST_CASE( 3, a4, 1, \ - la a0, foo; \ - add a1, a0, 1024; \ - lr.w a1, (a1); \ - sc.w a4, a1, (a0); \ -) - -# have each core add its coreid to foo 1000 times -la a0, foo -li a1, 1000 -1: lr.w a4, (a0) -add a4, a4, a2 -sc.w a4, a4, (a0) -bnez a4, 1b -add a1, a1, -1 -bnez a1, 1b - -# wait for all cores to finish -la a0, barrier -li a1, 1 -amoadd.w x0, a1, (a0) -1: lw a1, (a0) -blt a1, a3, 1b -fence - -# expected result is 1000*ncores*(ncores-1)/2 -TEST_CASE( 4, a2, 0, \ - la a0, foo; \ - li a1, 500; \ - mul a1, a1, a3; \ - add a2, a3, -1; \ - mul a1, a1, a2; \ - lw a2, (a0); \ - sub a2, a2, a1; \ -) - -TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -coreid: .word 0 -barrier: .word 0 -foo: .word 0 -RVTEST_DATA_END diff --git a/isa/rv64ui/mul.S b/isa/rv64ui/mul.S deleted file mode 100644 index c647e97..0000000 --- a/isa/rv64ui/mul.S +++ /dev/null @@ -1,78 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# mul.S -#----------------------------------------------------------------------------- -# -# Test mul instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP(32, mul, 0x0000000000001200, 0x0000000000007e00, 0x6db6db6db6db6db7 ); - TEST_RR_OP(33, mul, 0x0000000000001240, 0x0000000000007fc0, 0x6db6db6db6db6db7 ); - - TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, mul, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); - TEST_RR_OP( 6, mul, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); - TEST_RR_OP( 7, mul, 0x0000400000000000, 0xffffffff80000000, 0xffffffffffff8000 ); - - TEST_RR_OP(30, mul, 0x000000000000ff7f, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d ); - TEST_RR_OP(31, mul, 0x000000000000ff7f, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 ); - TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 ); - TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 ); - TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 ); - TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 ); - - TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 ); - TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 ); - TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 ); - TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 ); - TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 ); - TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 ); - - TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 ); - TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 ); - TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 ); - TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 ); - TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 ); - TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 ); - - TEST_RR_ZEROSRC1( 26, mul, 0, 31 ); - TEST_RR_ZEROSRC2( 27, mul, 0, 32 ); - TEST_RR_ZEROSRC12( 28, mul, 0 ); - TEST_RR_ZERODEST( 29, mul, 33, 34 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/mulh.S b/isa/rv64ui/mulh.S deleted file mode 100644 index 1fd12a1..0000000 --- a/isa/rv64ui/mulh.S +++ /dev/null @@ -1,72 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# mulh.S -#----------------------------------------------------------------------------- -# -# Test mulh instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, mulh, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); - TEST_RR_OP( 6, mulh, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); - TEST_RR_OP( 7, mulh, 0x0000000000000000, 0xffffffff80000000, 0xffffffffffff8000 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 8, mulh, 143, 13<<32, 11<<32 ); - TEST_RR_SRC2_EQ_DEST( 9, mulh, 154, 14<<32, 11<<32 ); - TEST_RR_SRC12_EQ_DEST( 10, mulh, 169, 13<<32 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 11, 0, mulh, 143, 13<<32, 11<<32 ); - TEST_RR_DEST_BYPASS( 12, 1, mulh, 154, 14<<32, 11<<32 ); - TEST_RR_DEST_BYPASS( 13, 2, mulh, 165, 15<<32, 11<<32 ); - - TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 143, 13<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 154, 14<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 165, 15<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 143, 13<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 154, 14<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 165, 15<<32, 11<<32 ); - - TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 143, 13<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 154, 14<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 165, 15<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 143, 13<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 154, 14<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 165, 15<<32, 11<<32 ); - - TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<32 ); - TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<32 ); - TEST_RR_ZEROSRC12( 28, mulh, 0 ); - TEST_RR_ZERODEST( 29, mulh, 33<<32, 34<<32 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/mulhsu.S b/isa/rv64ui/mulhsu.S deleted file mode 100644 index c037db2..0000000 --- a/isa/rv64ui/mulhsu.S +++ /dev/null @@ -1,72 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# mulhsu.S -#----------------------------------------------------------------------------- -# -# Test mulhsu instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, mulhsu, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); - TEST_RR_OP( 6, mulhsu, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); - TEST_RR_OP( 7, mulhsu, 0xffffffff80000000, 0xffffffff80000000, 0xffffffffffff8000 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 143, 13<<32, 11<<32 ); - TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 154, 14<<32, 11<<32 ); - TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 169, 13<<32 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 143, 13<<32, 11<<32 ); - TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 154, 14<<32, 11<<32 ); - TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 165, 15<<32, 11<<32 ); - - TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 143, 13<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 154, 14<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 165, 15<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 143, 13<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 154, 14<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 165, 15<<32, 11<<32 ); - - TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 143, 13<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 154, 14<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 165, 15<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 143, 13<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 154, 14<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 165, 15<<32, 11<<32 ); - - TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<32 ); - TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<32 ); - TEST_RR_ZEROSRC12( 28, mulhsu, 0 ); - TEST_RR_ZERODEST( 29, mulhsu, 33<<32, 34<<32 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/mulhu.S b/isa/rv64ui/mulhu.S deleted file mode 100644 index aa7b762..0000000 --- a/isa/rv64ui/mulhu.S +++ /dev/null @@ -1,75 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# mulhu.S -#----------------------------------------------------------------------------- -# -# Test mulhu instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, mulhu, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); - TEST_RR_OP( 6, mulhu, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); - TEST_RR_OP( 7, mulhu, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 ); - - TEST_RR_OP(30, mulhu, 0x000000000001fefe, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d ); - TEST_RR_OP(31, mulhu, 0x000000000001fefe, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 8, mulhu, 143, 13<<32, 11<<32 ); - TEST_RR_SRC2_EQ_DEST( 9, mulhu, 154, 14<<32, 11<<32 ); - TEST_RR_SRC12_EQ_DEST( 10, mulhu, 169, 13<<32 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 11, 0, mulhu, 143, 13<<32, 11<<32 ); - TEST_RR_DEST_BYPASS( 12, 1, mulhu, 154, 14<<32, 11<<32 ); - TEST_RR_DEST_BYPASS( 13, 2, mulhu, 165, 15<<32, 11<<32 ); - - TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 143, 13<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 154, 14<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 165, 15<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 143, 13<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 154, 14<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 165, 15<<32, 11<<32 ); - - TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 143, 13<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 154, 14<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 165, 15<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 143, 13<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 154, 14<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 165, 15<<32, 11<<32 ); - - TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<32 ); - TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<32 ); - TEST_RR_ZEROSRC12( 28, mulhu, 0 ); - TEST_RR_ZERODEST( 29, mulhu, 33<<32, 34<<32 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/mulw.S b/isa/rv64ui/mulw.S deleted file mode 100644 index 379c3f2..0000000 --- a/isa/rv64ui/mulw.S +++ /dev/null @@ -1,72 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# mulw.S -#----------------------------------------------------------------------------- -# -# Test mulw instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, mulw, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, mulw, 0x00000001, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, mulw, 0x00000015, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, mulw, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); - TEST_RR_OP( 6, mulw, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); - TEST_RR_OP( 7, mulw, 0x0000000000000000, 0xffffffff80000000, 0xffffffffffff8000 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 8, mulw, 143, 13, 11 ); - TEST_RR_SRC2_EQ_DEST( 9, mulw, 154, 14, 11 ); - TEST_RR_SRC12_EQ_DEST( 10, mulw, 169, 13 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 11, 0, mulw, 143, 13, 11 ); - TEST_RR_DEST_BYPASS( 12, 1, mulw, 154, 14, 11 ); - TEST_RR_DEST_BYPASS( 13, 2, mulw, 165, 15, 11 ); - - TEST_RR_SRC12_BYPASS( 14, 0, 0, mulw, 143, 13, 11 ); - TEST_RR_SRC12_BYPASS( 15, 0, 1, mulw, 154, 14, 11 ); - TEST_RR_SRC12_BYPASS( 16, 0, 2, mulw, 165, 15, 11 ); - TEST_RR_SRC12_BYPASS( 17, 1, 0, mulw, 143, 13, 11 ); - TEST_RR_SRC12_BYPASS( 18, 1, 1, mulw, 154, 14, 11 ); - TEST_RR_SRC12_BYPASS( 19, 2, 0, mulw, 165, 15, 11 ); - - TEST_RR_SRC21_BYPASS( 20, 0, 0, mulw, 143, 13, 11 ); - TEST_RR_SRC21_BYPASS( 21, 0, 1, mulw, 154, 14, 11 ); - TEST_RR_SRC21_BYPASS( 22, 0, 2, mulw, 165, 15, 11 ); - TEST_RR_SRC21_BYPASS( 23, 1, 0, mulw, 143, 13, 11 ); - TEST_RR_SRC21_BYPASS( 24, 1, 1, mulw, 154, 14, 11 ); - TEST_RR_SRC21_BYPASS( 25, 2, 0, mulw, 165, 15, 11 ); - - TEST_RR_ZEROSRC1( 26, mulw, 0, 31 ); - TEST_RR_ZEROSRC2( 27, mulw, 0, 32 ); - TEST_RR_ZEROSRC12( 28, mulw, 0 ); - TEST_RR_ZERODEST( 29, mulw, 33, 34 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/rem.S b/isa/rv64ui/rem.S deleted file mode 100644 index e3248ff..0000000 --- a/isa/rv64ui/rem.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# rem.S -#----------------------------------------------------------------------------- -# -# Test rem instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, rem, 2, 20, 6 ); - TEST_RR_OP( 3, rem, -2, -20, 6 ); - TEST_RR_OP( 4, rem, 2, 20, -6 ); - TEST_RR_OP( 5, rem, -2, -20, -6 ); - - TEST_RR_OP( 6, rem, 0, -1<<63, 1 ); - TEST_RR_OP( 7, rem, 0, -1<<63, -1 ); - - TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 ); - TEST_RR_OP( 9, rem, 1, 1, 0 ); - TEST_RR_OP(10, rem, 0, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/remu.S b/isa/rv64ui/remu.S deleted file mode 100644 index 6946d0d..0000000 --- a/isa/rv64ui/remu.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# remu.S -#----------------------------------------------------------------------------- -# -# Test remu instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, remu, 2, 20, 6 ); - TEST_RR_OP( 3, remu, 2, -20, 6 ); - TEST_RR_OP( 4, remu, 20, 20, -6 ); - TEST_RR_OP( 5, remu, -20, -20, -6 ); - - TEST_RR_OP( 6, remu, 0, -1<<63, 1 ); - TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 ); - - TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 ); - TEST_RR_OP( 9, remu, 1, 1, 0 ); - TEST_RR_OP(10, remu, 0, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/remuw.S b/isa/rv64ui/remuw.S deleted file mode 100644 index 334b5c5..0000000 --- a/isa/rv64ui/remuw.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# remuw.S -#----------------------------------------------------------------------------- -# -# Test remuw instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, remuw, 2, 20, 6 ); - TEST_RR_OP( 3, remuw, 2, -20, 6 ); - TEST_RR_OP( 4, remuw, 20, 20, -6 ); - TEST_RR_OP( 5, remuw, -20, -20, -6 ); - - TEST_RR_OP( 6, remuw, 0, -1<<31, 1 ); - TEST_RR_OP( 7, remuw, -1<<31, -1<<31, -1 ); - - TEST_RR_OP( 8, remuw, -1<<31, -1<<31, 0 ); - TEST_RR_OP( 9, remuw, 1, 1, 0 ); - TEST_RR_OP(10, remuw, 0, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/remw.S b/isa/rv64ui/remw.S deleted file mode 100644 index 3ae8e3d..0000000 --- a/isa/rv64ui/remw.S +++ /dev/null @@ -1,42 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# remw.S -#----------------------------------------------------------------------------- -# -# Test remw instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, remw, 2, 20, 6 ); - TEST_RR_OP( 3, remw, -2, -20, 6 ); - TEST_RR_OP( 4, remw, 2, 20, -6 ); - TEST_RR_OP( 5, remw, -2, -20, -6 ); - - TEST_RR_OP( 6, remw, 0, -1<<31, 1 ); - TEST_RR_OP( 7, remw, 0, -1<<31, -1 ); - - TEST_RR_OP( 8, remw, -1<<31, -1<<31, 0 ); - TEST_RR_OP( 9, remw, 1, 1, 0 ); - TEST_RR_OP(10, remw, 0, 0, 0 ); - TEST_RR_OP(11, remw, 0xfffffffffffff897,0xfffffffffffff897, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64um/Makefrag b/isa/rv64um/Makefrag new file mode 100644 index 0000000..360bd7a --- /dev/null +++ b/isa/rv64um/Makefrag @@ -0,0 +1,13 @@ +#======================================================================= +# Makefrag for rv64um tests +#----------------------------------------------------------------------- + +rv64um_sc_tests = \ + div divu divuw divw \ + mul mulh mulhsu mulhu mulw \ + rem remu remuw remw \ + +rv64um_p_tests = $(addprefix rv64um-p-, $(rv64um_sc_tests)) +rv64um_v_tests = $(addprefix rv64um-v-, $(rv64um_sc_tests)) + +spike_tests += $(rv64um_p_tests) $(rv64um_v_tests) diff --git a/isa/rv64um/div.S b/isa/rv64um/div.S new file mode 100644 index 0000000..ee21f0c --- /dev/null +++ b/isa/rv64um/div.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# div.S +#----------------------------------------------------------------------------- +# +# Test div instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, div, 3, 20, 6 ); + TEST_RR_OP( 3, div, -3, -20, 6 ); + TEST_RR_OP( 4, div, -3, 20, -6 ); + TEST_RR_OP( 5, div, 3, -20, -6 ); + + TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 ); + TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 ); + + TEST_RR_OP( 8, div, -1, -1<<63, 0 ); + TEST_RR_OP( 9, div, -1, 1, 0 ); + TEST_RR_OP(10, div, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/divu.S b/isa/rv64um/divu.S new file mode 100644 index 0000000..e63fd65 --- /dev/null +++ b/isa/rv64um/divu.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# divu.S +#----------------------------------------------------------------------------- +# +# Test divu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, divu, 3, 20, 6 ); + TEST_RR_OP( 3, divu, 3074457345618258599, -20, 6 ); + TEST_RR_OP( 4, divu, 0, 20, -6 ); + TEST_RR_OP( 5, divu, 0, -20, -6 ); + + TEST_RR_OP( 6, divu, -1<<63, -1<<63, 1 ); + TEST_RR_OP( 7, divu, 0, -1<<63, -1 ); + + TEST_RR_OP( 8, divu, -1, -1<<63, 0 ); + TEST_RR_OP( 9, divu, -1, 1, 0 ); + TEST_RR_OP(10, divu, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/divuw.S b/isa/rv64um/divuw.S new file mode 100644 index 0000000..4c9eee7 --- /dev/null +++ b/isa/rv64um/divuw.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# divuw.S +#----------------------------------------------------------------------------- +# +# Test divuw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, divuw, 3, 20, 6 ); + TEST_RR_OP( 3, divuw, 715827879, -20 << 32 >> 32, 6 ); + TEST_RR_OP( 4, divuw, 0, 20, -6 ); + TEST_RR_OP( 5, divuw, 0, -20, -6 ); + + TEST_RR_OP( 6, divuw, -1<<31, -1<<31, 1 ); + TEST_RR_OP( 7, divuw, 0, -1<<31, -1 ); + + TEST_RR_OP( 8, divuw, -1, -1<<31, 0 ); + TEST_RR_OP( 9, divuw, -1, 1, 0 ); + TEST_RR_OP(10, divuw, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/divw.S b/isa/rv64um/divw.S new file mode 100644 index 0000000..4cffa1a --- /dev/null +++ b/isa/rv64um/divw.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# divw.S +#----------------------------------------------------------------------------- +# +# Test divw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, divw, 3, 20, 6 ); + TEST_RR_OP( 3, divw, -3, -20, 6 ); + TEST_RR_OP( 4, divw, -3, 20, -6 ); + TEST_RR_OP( 5, divw, 3, -20, -6 ); + + TEST_RR_OP( 6, divw, -1<<31, -1<<31, 1 ); + TEST_RR_OP( 7, divw, -1<<31, -1<<31, -1 ); + + TEST_RR_OP( 8, divw, -1, -1<<31, 0 ); + TEST_RR_OP( 9, divw, -1, 1, 0 ); + TEST_RR_OP(10, divw, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/mul.S b/isa/rv64um/mul.S new file mode 100644 index 0000000..c647e97 --- /dev/null +++ b/isa/rv64um/mul.S @@ -0,0 +1,78 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mul.S +#----------------------------------------------------------------------------- +# +# Test mul instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, mul, 0x0000000000001200, 0x0000000000007e00, 0x6db6db6db6db6db7 ); + TEST_RR_OP(33, mul, 0x0000000000001240, 0x0000000000007fc0, 0x6db6db6db6db6db7 ); + + TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mul, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, mul, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, mul, 0x0000400000000000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP(30, mul, 0x000000000000ff7f, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d ); + TEST_RR_OP(31, mul, 0x000000000000ff7f, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, mul, 0, 31 ); + TEST_RR_ZEROSRC2( 27, mul, 0, 32 ); + TEST_RR_ZEROSRC12( 28, mul, 0 ); + TEST_RR_ZERODEST( 29, mul, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/mulh.S b/isa/rv64um/mulh.S new file mode 100644 index 0000000..1fd12a1 --- /dev/null +++ b/isa/rv64um/mulh.S @@ -0,0 +1,72 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulh.S +#----------------------------------------------------------------------------- +# +# Test mulh instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulh, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, mulh, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, mulh, 0x0000000000000000, 0xffffffff80000000, 0xffffffffffff8000 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulh, 143, 13<<32, 11<<32 ); + TEST_RR_SRC2_EQ_DEST( 9, mulh, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_EQ_DEST( 10, mulh, 169, 13<<32 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulh, 143, 13<<32, 11<<32 ); + TEST_RR_DEST_BYPASS( 12, 1, mulh, 154, 14<<32, 11<<32 ); + TEST_RR_DEST_BYPASS( 13, 2, mulh, 165, 15<<32, 11<<32 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 143, 13<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 165, 15<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 143, 13<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 165, 15<<32, 11<<32 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 143, 13<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 154, 14<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 165, 15<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 143, 13<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 154, 14<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 165, 15<<32, 11<<32 ); + + TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<32 ); + TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<32 ); + TEST_RR_ZEROSRC12( 28, mulh, 0 ); + TEST_RR_ZERODEST( 29, mulh, 33<<32, 34<<32 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/mulhsu.S b/isa/rv64um/mulhsu.S new file mode 100644 index 0000000..c037db2 --- /dev/null +++ b/isa/rv64um/mulhsu.S @@ -0,0 +1,72 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulhsu.S +#----------------------------------------------------------------------------- +# +# Test mulhsu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulhsu, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, mulhsu, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, mulhsu, 0xffffffff80000000, 0xffffffff80000000, 0xffffffffffff8000 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 169, 13<<32 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 143, 13<<32, 11<<32 ); + TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 154, 14<<32, 11<<32 ); + TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 165, 15<<32, 11<<32 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 165, 15<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 165, 15<<32, 11<<32 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 165, 15<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 165, 15<<32, 11<<32 ); + + TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<32 ); + TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<32 ); + TEST_RR_ZEROSRC12( 28, mulhsu, 0 ); + TEST_RR_ZERODEST( 29, mulhsu, 33<<32, 34<<32 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/mulhu.S b/isa/rv64um/mulhu.S new file mode 100644 index 0000000..aa7b762 --- /dev/null +++ b/isa/rv64um/mulhu.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulhu.S +#----------------------------------------------------------------------------- +# +# Test mulhu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulhu, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, mulhu, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, mulhu, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP(30, mulhu, 0x000000000001fefe, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d ); + TEST_RR_OP(31, mulhu, 0x000000000001fefe, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulhu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC2_EQ_DEST( 9, mulhu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_EQ_DEST( 10, mulhu, 169, 13<<32 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulhu, 143, 13<<32, 11<<32 ); + TEST_RR_DEST_BYPASS( 12, 1, mulhu, 154, 14<<32, 11<<32 ); + TEST_RR_DEST_BYPASS( 13, 2, mulhu, 165, 15<<32, 11<<32 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 165, 15<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 165, 15<<32, 11<<32 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 165, 15<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 165, 15<<32, 11<<32 ); + + TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<32 ); + TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<32 ); + TEST_RR_ZEROSRC12( 28, mulhu, 0 ); + TEST_RR_ZERODEST( 29, mulhu, 33<<32, 34<<32 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/mulw.S b/isa/rv64um/mulw.S new file mode 100644 index 0000000..379c3f2 --- /dev/null +++ b/isa/rv64um/mulw.S @@ -0,0 +1,72 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulw.S +#----------------------------------------------------------------------------- +# +# Test mulw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulw, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulw, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulw, 0x00000015, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulw, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, mulw, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, mulw, 0x0000000000000000, 0xffffffff80000000, 0xffffffffffff8000 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulw, 143, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, mulw, 154, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, mulw, 169, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulw, 143, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, mulw, 154, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, mulw, 165, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulw, 143, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulw, 154, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulw, 165, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulw, 143, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulw, 154, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulw, 165, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulw, 143, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulw, 154, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulw, 165, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulw, 143, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulw, 154, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulw, 165, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, mulw, 0, 31 ); + TEST_RR_ZEROSRC2( 27, mulw, 0, 32 ); + TEST_RR_ZEROSRC12( 28, mulw, 0 ); + TEST_RR_ZERODEST( 29, mulw, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/rem.S b/isa/rv64um/rem.S new file mode 100644 index 0000000..e3248ff --- /dev/null +++ b/isa/rv64um/rem.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rem.S +#----------------------------------------------------------------------------- +# +# Test rem instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rem, 2, 20, 6 ); + TEST_RR_OP( 3, rem, -2, -20, 6 ); + TEST_RR_OP( 4, rem, 2, 20, -6 ); + TEST_RR_OP( 5, rem, -2, -20, -6 ); + + TEST_RR_OP( 6, rem, 0, -1<<63, 1 ); + TEST_RR_OP( 7, rem, 0, -1<<63, -1 ); + + TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 ); + TEST_RR_OP( 9, rem, 1, 1, 0 ); + TEST_RR_OP(10, rem, 0, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/remu.S b/isa/rv64um/remu.S new file mode 100644 index 0000000..6946d0d --- /dev/null +++ b/isa/rv64um/remu.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# remu.S +#----------------------------------------------------------------------------- +# +# Test remu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, remu, 2, 20, 6 ); + TEST_RR_OP( 3, remu, 2, -20, 6 ); + TEST_RR_OP( 4, remu, 20, 20, -6 ); + TEST_RR_OP( 5, remu, -20, -20, -6 ); + + TEST_RR_OP( 6, remu, 0, -1<<63, 1 ); + TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 ); + + TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 ); + TEST_RR_OP( 9, remu, 1, 1, 0 ); + TEST_RR_OP(10, remu, 0, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/remuw.S b/isa/rv64um/remuw.S new file mode 100644 index 0000000..334b5c5 --- /dev/null +++ b/isa/rv64um/remuw.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# remuw.S +#----------------------------------------------------------------------------- +# +# Test remuw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, remuw, 2, 20, 6 ); + TEST_RR_OP( 3, remuw, 2, -20, 6 ); + TEST_RR_OP( 4, remuw, 20, 20, -6 ); + TEST_RR_OP( 5, remuw, -20, -20, -6 ); + + TEST_RR_OP( 6, remuw, 0, -1<<31, 1 ); + TEST_RR_OP( 7, remuw, -1<<31, -1<<31, -1 ); + + TEST_RR_OP( 8, remuw, -1<<31, -1<<31, 0 ); + TEST_RR_OP( 9, remuw, 1, 1, 0 ); + TEST_RR_OP(10, remuw, 0, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/remw.S b/isa/rv64um/remw.S new file mode 100644 index 0000000..3ae8e3d --- /dev/null +++ b/isa/rv64um/remw.S @@ -0,0 +1,42 @@ +# See LICENSE for license details. + +#***************************************************************************** +# remw.S +#----------------------------------------------------------------------------- +# +# Test remw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, remw, 2, 20, 6 ); + TEST_RR_OP( 3, remw, -2, -20, 6 ); + TEST_RR_OP( 4, remw, 2, 20, -6 ); + TEST_RR_OP( 5, remw, -2, -20, -6 ); + + TEST_RR_OP( 6, remw, 0, -1<<31, 1 ); + TEST_RR_OP( 7, remw, 0, -1<<31, -1 ); + + TEST_RR_OP( 8, remw, -1<<31, -1<<31, 0 ); + TEST_RR_OP( 9, remw, 1, 1, 0 ); + TEST_RR_OP(10, remw, 0, 0, 0 ); + TEST_RR_OP(11, remw, 0xfffffffffffff897,0xfffffffffffff897, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END -- cgit v1.1