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2024-01-29Uses appropriate addi instruction in lrsc test.Lucas Clemente Vella1-1/+1
2023-04-06Augment LR/SC test to test that SC-after-failed-SC failsAndrew Waterman1-2/+5
2023-04-06Merge pull request #466 from riscv-software-src/spike-zicntrAndrew Waterman1-2/+2
Include Zicntr in Spike ISA string
2023-04-06Merge pull request #464 from nervosnetwork/amocmp_wAndrew Waterman4-1/+40
Add more tests for amo[max/maxu/min/minu]_w
2023-04-06Include Zicntr in Spike ISA stringAndrew Waterman1-2/+2
Spike no longer enables Zicntr by default, so turn it on explicitly. cc @jerryz123
2023-04-06Add more tests for amomax/maxu/min/minu_wmohanson4-1/+40
2023-03-16Fix breakpoint.S failing when tcontrol is implemented (#463)Luke Wren1-0/+10
2023-02-27rv32ui test misaligned load/store data (#459)Jesse Taube3-5/+9
2023-02-13Fix ma_fetch test for norvc (#454)Yujia Qiao1-1/+1
The trap handler for norvc systems has an incorrect jump offset Signed-off-by: Yujia Qiao <code@rapiz.me>
2023-01-19Fix ma_fetch test for writable misa.C (#449)Jerry Zhao1-3/+3
2023-01-19Pass --misaligned flag to Spike to run ISA tests (#445)Andrew Waterman1-2/+2
...because the ma_data test requires this feature. Don't merge until https://github.com/riscv-software-src/riscv-isa-sim/pull/1206 is merged.
2022-12-28Fix ma_fetch test to support systems where no RVC does not imply IALIGN=32Jerry Zhao1-9/+31
2022-12-07zicntr: separate cycle/instret accessibility test (#439)Chih-Min Chao5-16/+69
It is allowed that M-mode only implementation could skip cycle/instret if the Zicntr is not included. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2022-09-27rv64ui test misaligned load/store data (#410)John Ingalls2-0/+388
2022-09-27zicboz: comment # (#412)John Ingalls1-1/+1
2022-09-26zicbo test zero (#411)John Ingalls3-2/+49
2022-06-09Test misaligned stores. (#397)Tim Newsome8-0/+158
Assume that misaligned loads work correctly. Passes `make -C isa run` against spike (both with and without misaligned support).
2022-06-07Test misaligned loads.Tim Newsome8-0/+160
Cover lh, lw, and ld (only on rv64).
2022-06-07Set TESTNUM before executing code.Tim Newsome3-6/+4
Tests that might cause a trap during their code need TESTNUM (gp) set so the trap handler can correctly identify which test is running, and also report that to the user in case the test fails. Fix up shamt.S and csr.S to handle the new behavior.
2022-06-06Revert unaligned tests.Tim Newsome3-51/+1
They lead to two problems: 1. The change to set TESTNUM before the test instead of after broke a few tests that relied on the old behavior. 2. Some tests in the v variant do something in the exception handler such that when they get an unaligned access exception, they end up stuck in a loop of unaligned access exceptions and the exception handler set up in the test is never called.
2022-06-06Test unaligned ld accesses.Tim Newsome1-0/+27
Identical to the lw change in #391.
2022-06-06Add unaligned test cases for lwTim Newsome1-0/+23
The test passes if either the target register contains the correct value, or the target raises a misaligned load exception.
2022-06-06Set TESTNUM before executing code.Tim Newsome1-1/+1
Tests that might cause a trap during their code need TESTNUM (gp) set so the trap handler can correctly identify which test is running, and also report that to the user in case the test fails.
2022-05-28Permit mtval to be zero in misaligned address test, fixes #389 (#390)Luke Wren1-0/+2
2022-03-08Add Zfh and Svnapot to Spike ISA stringAndrew Waterman1-2/+2
Otherwise, "make run" doesn't work.
2021-07-22Fix #352 (#353)Daniel Lustig1-2/+2
Thanks to @pdonahue-ventana for pointing this out
2021-07-21Move the Svnapot test to its own folder (#351)Daniel Lustig4-1/+10
...since not all implementations will support it
2021-07-19Add a test for Svnapot (#349)Daniel Lustig2-0/+173
2021-06-01Enable access to cycle counter before trying to write itAndrew Waterman1-0/+13
There are two reasons that writing the cycle counter might trap: - Because it's a read-only CSR - Because mcounteren.CY=0 or scounteren.CY=0 We want to make sure we're testing the first property, so set up the other bits accordingly.
2021-06-01Test all four ways of reading a read-only CSRAndrew Waterman1-0/+8
2021-05-12Fix for rv64mi/sbreak and rv64mi/scall that I broke in my previous commit: ↵SLAMET RIANTO2-0/+2
(#337) Added "#define stvec mtvec" under __MACHINE_MODE ifdef. Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com>
2021-05-10Fixes for illegal.S to support Bare-SMode and sbreak.S & scall.S to support ↵SLAMET RIANTO3-0/+52
CLIC mode. (#336) illegal.S: - After the test enters supervisor mode, check if paging is supported. - If paging is NOT supported (i.e. Bare S-mode), jump to a new section of code that checks the following: -- SFENCE.VMA causing illegal instruction trap regardless of TVM. -- Access to SATP does not trap. -- Jump to the same TSR check as regular S-mode -- End test sbreak.S & scall.S: - Before checking for scause, check if the core is in CLIC-mode (mtvec[1]). - If we're in CLIC-mode, mask off scause bits[(XLEN-1):8] before checing its value. - Otherwise, don't mask off any scause bits as in the original test. Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com>
2021-02-01Align mtvec in rv32mi-p-shamt testAndrew Waterman1-0/+1
Resolves #323
2021-01-08Don't rely on the implementation-specific WFI time limit (#318)Paul Donahue1-18/+0
* Bump riscv-test-env * Merge master * Don't assume that mscratch is initialized to a particular value on reset * Remove testcase that relies on the implementation-specific WFI time limit being 0.
2021-01-04Disable rv32ua/rv64ua LR/SC test case 4 (#316)Ben Marshall1-8/+14
- After discussion in riscv/riscv-tests#315, disable this test case, as it makes implementation assumptions which are not valid with respect to the specification. - Leave code present but commented out. On branch dev/benm-disable-lrsc-test-4 Changes to be committed: modified: isa/rv64ua/lrsc.S
2020-12-16Refactor rv64ud structural test to match format of other tests (#311)Kathlene Hurt1-11/+13
* Refactored rv64ud structural test to use pass/fail macros and test numbers * More clean up so test actually jumps to fail label
2020-12-08Add rd=x0 test case to csr test (#308)Takahiro1-0/+1
2020-12-07Fix minor typo (#307)Takahiro1-1/+1
2020-11-20Only attempt to build tests supported by compilerAndrew Waterman19-38/+6
Resolves #303
2020-11-11add zfh (float16) test case and related macros (#301)Chih-Min Chao26-0/+769
* ext: add zfh extension test case and related macro Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * build: add zfh to target Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-10-19use registers present on rv32e (#299)Sandeep Rajendran1-4/+4
2020-03-21Fix regression introduced by 24d7d6b68c5581c36cbdef354b1882a7a8dd52c5Andrew Waterman1-7/+7
2020-03-21Move self-modifying 'fence.i' ops to .data memory section (#269)WRansohoff1-6/+14
Co-authored-by: WRR <-@->
2020-03-19Fix comments error in fmin.S (#267)Mohanson2-4/+4
2020-03-18Have both rs=rd and rs!=rd cases in csr.S (#263)Takahiro1-12/+15
2020-03-18Fix shamt.S header (#264)Takahiro1-2/+2
2020-03-16Add a test case rs = rd to jalr.S (#258)Takahiro1-0/+16
2020-03-11Add comment explaining convoluted rv64mi-p-scall behaviorAndrew Waterman1-0/+6
2020-03-11Revert "scall: make the intention of the test in machine mode more clear (#246)"Andrew Waterman1-6/+1
This reverts commit 6fa1896b2a3f581359f0b6a952542f814e30602c. Resolves #256
2020-03-11Setup a multilevel page table to avoid misaligned superpages caused by ↵Cedric Orban1-0/+4
variable DRAM_BASE (#255) * setup a multilevel page table to avoid misaligned superpages * Revert "setup a multilevel page table to avoid misaligned superpages" This reverts commit 73c142df7dbdd3a5347ef228a368fb58b0b12be5. * statically fail if DRAM_BASE is not superpage-aligned
generated by cgit v1.1 at 2024-07-16 20:18:45 +0000