Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2022-05-27 | Remove ineffective tests.trigger_priority | Tim Newsome | 1 | -2/+0 | |
2022-05-25 | Address trigger has higher priority than alignment | Tim Newsome | 1 | -0/+46 | |
Used this test to confirm that https://github.com/riscv-software-src/riscv-isa-sim/pull/1013 works right. | |||||
2022-03-08 | Add Zfh and Svnapot to Spike ISA string | Andrew Waterman | 1 | -2/+2 | |
Otherwise, "make run" doesn't work. | |||||
2021-07-22 | Fix #352 (#353) | Daniel Lustig | 1 | -2/+2 | |
Thanks to @pdonahue-ventana for pointing this out | |||||
2021-07-21 | Move the Svnapot test to its own folder (#351) | Daniel Lustig | 4 | -1/+10 | |
...since not all implementations will support it | |||||
2021-07-19 | Add a test for Svnapot (#349) | Daniel Lustig | 2 | -0/+173 | |
2021-06-01 | Enable access to cycle counter before trying to write it | Andrew Waterman | 1 | -0/+13 | |
There are two reasons that writing the cycle counter might trap: - Because it's a read-only CSR - Because mcounteren.CY=0 or scounteren.CY=0 We want to make sure we're testing the first property, so set up the other bits accordingly. | |||||
2021-06-01 | Test all four ways of reading a read-only CSR | Andrew Waterman | 1 | -0/+8 | |
2021-05-12 | Fix for rv64mi/sbreak and rv64mi/scall that I broke in my previous commit: ↵ | SLAMET RIANTO | 2 | -0/+2 | |
(#337) Added "#define stvec mtvec" under __MACHINE_MODE ifdef. Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com> | |||||
2021-05-10 | Fixes for illegal.S to support Bare-SMode and sbreak.S & scall.S to support ↵ | SLAMET RIANTO | 3 | -0/+52 | |
CLIC mode. (#336) illegal.S: - After the test enters supervisor mode, check if paging is supported. - If paging is NOT supported (i.e. Bare S-mode), jump to a new section of code that checks the following: -- SFENCE.VMA causing illegal instruction trap regardless of TVM. -- Access to SATP does not trap. -- Jump to the same TSR check as regular S-mode -- End test sbreak.S & scall.S: - Before checking for scause, check if the core is in CLIC-mode (mtvec[1]). - If we're in CLIC-mode, mask off scause bits[(XLEN-1):8] before checing its value. - Otherwise, don't mask off any scause bits as in the original test. Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com> | |||||
2021-02-01 | Align mtvec in rv32mi-p-shamt test | Andrew Waterman | 1 | -0/+1 | |
Resolves #323 | |||||
2021-01-08 | Don't rely on the implementation-specific WFI time limit (#318) | Paul Donahue | 1 | -18/+0 | |
* Bump riscv-test-env * Merge master * Don't assume that mscratch is initialized to a particular value on reset * Remove testcase that relies on the implementation-specific WFI time limit being 0. | |||||
2021-01-04 | Disable rv32ua/rv64ua LR/SC test case 4 (#316) | Ben Marshall | 1 | -8/+14 | |
- After discussion in riscv/riscv-tests#315, disable this test case, as it makes implementation assumptions which are not valid with respect to the specification. - Leave code present but commented out. On branch dev/benm-disable-lrsc-test-4 Changes to be committed: modified: isa/rv64ua/lrsc.S | |||||
2020-12-16 | Refactor rv64ud structural test to match format of other tests (#311) | Kathlene Hurt | 1 | -11/+13 | |
* Refactored rv64ud structural test to use pass/fail macros and test numbers * More clean up so test actually jumps to fail label | |||||
2020-12-08 | Add rd=x0 test case to csr test (#308) | Takahiro | 1 | -0/+1 | |
2020-12-07 | Fix minor typo (#307) | Takahiro | 1 | -1/+1 | |
2020-11-20 | Only attempt to build tests supported by compiler | Andrew Waterman | 19 | -38/+6 | |
Resolves #303 | |||||
2020-11-11 | add zfh (float16) test case and related macros (#301) | Chih-Min Chao | 26 | -0/+769 | |
* ext: add zfh extension test case and related macro Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * build: add zfh to target Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-10-19 | use registers present on rv32e (#299) | Sandeep Rajendran | 1 | -4/+4 | |
2020-03-21 | Fix regression introduced by 24d7d6b68c5581c36cbdef354b1882a7a8dd52c5 | Andrew Waterman | 1 | -7/+7 | |
2020-03-21 | Move self-modifying 'fence.i' ops to .data memory section (#269) | WRansohoff | 1 | -6/+14 | |
Co-authored-by: WRR <-@-> | |||||
2020-03-19 | Fix comments error in fmin.S (#267) | Mohanson | 2 | -4/+4 | |
2020-03-18 | Have both rs=rd and rs!=rd cases in csr.S (#263) | Takahiro | 1 | -12/+15 | |
2020-03-18 | Fix shamt.S header (#264) | Takahiro | 1 | -2/+2 | |
2020-03-16 | Add a test case rs = rd to jalr.S (#258) | Takahiro | 1 | -0/+16 | |
2020-03-11 | Add comment explaining convoluted rv64mi-p-scall behavior | Andrew Waterman | 1 | -0/+6 | |
2020-03-11 | Revert "scall: make the intention of the test in machine mode more clear (#246)" | Andrew Waterman | 1 | -6/+1 | |
This reverts commit 6fa1896b2a3f581359f0b6a952542f814e30602c. Resolves #256 | |||||
2020-03-11 | Setup a multilevel page table to avoid misaligned superpages caused by ↵ | Cedric Orban | 1 | -0/+4 | |
variable DRAM_BASE (#255) * setup a multilevel page table to avoid misaligned superpages * Revert "setup a multilevel page table to avoid misaligned superpages" This reverts commit 73c142df7dbdd3a5347ef228a368fb58b0b12be5. * statically fail if DRAM_BASE is not superpage-aligned | |||||
2020-03-06 | Don't assume reset state of mscratch (#254) | Paul Donahue | 1 | -1/+1 | |
* Bump riscv-test-env * Merge master * Don't assume that mscratch is initialized to a particular value on reset | |||||
2020-03-02 | enable rv32e compatability by replacing reg x29 with reg x7 (#250) | Cedric Orban | 1 | -12/+12 | |
2020-02-21 | scall: make the intention of the test in machine mode more clear (#246) | Nils Asmussen | 1 | -1/+6 | |
2020-02-20 | Fix rv64mi-p-csr on systems with FPUs | Andrew Waterman | 1 | -2/+3 | |
3a98ec2e306938cce07ab15e3678d670611aa66d introduced a subtle bug because of the value of TESTNUM at the point an expected exception was taken. Fix by moving the new tests earlier in the program. | |||||
2020-01-31 | Added CSR test cases on whether writing 0 to CSR works, as that might get ↵ | Torbjørn Viem Ness | 1 | -0/+2 | |
overlooked by implementors because some CSR operations should ignore writes if source is x0 (#236) | |||||
2019-11-04 | Remove cruft from icache-alias test | Andrew Waterman | 1 | -35/+0 | |
2019-11-04 | Add rv64si-p-icache-alias | Andrew Waterman | 2 | -0/+177 | |
This test checks that an I$ appears to be physically indexed. | |||||
2019-07-29 | Support RV32E. Fixed #198 (#200) | Leway Colin | 3 | -42/+42 | |
2019-04-20 | masking no longer required. | Neel | 1 | -16/+0 | |
2019-04-20 | removing check for reset value of type in mcontrol | Neel | 1 | -10/+8 | |
2019-04-20 | fix for #159 #158 | Neel | 1 | -4/+7 | |
2019-03-17 | Rename TEST_SRL to TEST_SRLI to avoid conflicts with another TEST_SRL (#183) | Pavel I. Kryukov | 1 | -18/+18 | |
2019-01-26 | Fix comments for shift amount. (#177) | takeoverjp | 3 | -3/+3 | |
2018-12-18 | Avoid using t3 and t4 for supporting RV32E (#173) | zhonghochen | 1 | -5/+6 | |
2018-11-16 | Test memory content on failing SC (#171) | Florian Zaruba | 1 | -4/+10 | |
2018-09-08 | RV64 s{ll,ra,rl}w tests with non-canonical values | Tommy Thorn | 6 | -0/+42 | |
2018-09-06 | Revert "breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) ↵ | Andrew Waterman | 1 | -1/+1 | |
(#159)" This reverts commit 901a2694d5384e4ef9af8e4fb0c9a07eb24d0028, under the advisement of @tommythorn in #158. | |||||
2018-09-06 | breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) (#159) | Tommy Thorn | 1 | -1/+1 | |
2018-08-21 | Changing the register mstatus is read into (#152) | Srivatsa Yogendra | 1 | -2/+2 | |
The mstatus reading overwrites the expected user mode cause value. | |||||
2018-08-20 | Revert "Fix to solve the failing tests shamt, csr and scall (#151)" | Andrew Waterman | 2 | -52/+5 | |
This reverts commit 31a91823b7c7becacd06c9c32e44180eea5e4fe7. These changes should be made to the test environment, not the tests themselves. | |||||
2018-08-17 | Fix to solve the failing tests shamt, csr and scall (#151) | Srivatsa Yogendra | 2 | -5/+52 | |
* making mtvec_handler global * Adding the pmp configuration inst The PMP config instructions are added as the test jumps to user mode * Adding pmp config inst Adding pmp config instructions as the test jumps to user mode * changing to PMP macros * changing to PMP Macros * moving the #endif after pmp initialization * Removing the unwanted label | |||||
2018-08-17 | making mtvec_handler global (#150) | Srivatsa Yogendra | 1 | -0/+1 | |