index
:
riscv-tools/riscv-tests.git
attempt-travis-fix
ceasetest2
compliance_tests
cs152-sp18-lab3
debug
debug-0.13
debug-clear-satp
debug-delete-sim
debug_auth
debug_disassemble
disable_unavailable
dma-memcpy
eos20-bringup
hw_watchpoint
interrupts
master
misc
no_progbuf
priv
privchange-dontdeleteme
python3
rekall
resume_from_trigger
riscv-tests-sail
rtos
rvt-master
smi-demo
split-isa-tests
sqrt-171
tmp
trap_entry_align
trap_entry_align-1
travis-dev
trigger_priority
usb_error
xlen_fix
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
isa
/
rv64uv
Age
Commit message (
Expand
)
Author
Files
Lines
2014-01-31
Reference TESTNUM instead of x28 directly
Andrew Waterman
50
-103
/
+103
2014-01-20
Add packed vvadd test for confprec Hwacha
Quan Nguyen
2
-0
/
+106
2013-11-28
Fix load offsets for the vvadd_fw test
Albert Ou
1
-3
/
+3
2013-11-19
Add rv64uv-p-amoxor_{w,d} tests
Quan Nguyen
3
-2
/
+118
2013-11-19
fix rv64uv/vvadd_fd test to correctly check results
Yunsup Lee
1
-2
/
+2
2013-11-05
correctly set SR_EA bit for all vector physical tests
Yunsup Lee
59
-59
/
+59
2013-10-18
revamp pt tests as well
Yunsup Lee
1
-1
/
+1
2013-10-18
hwacha virtual tests working
Yunsup Lee
1
-1
/
+1
2013-10-17
disable vector bank tests
Yunsup Lee
3
-594
/
+594
2013-10-17
add passing physical vector tests back in
Yunsup Lee
1
-2
/
+1
2013-10-17
update out-of-date floating-point test in rv64uv
Yunsup Lee
1
-1
/
+1
2013-10-17
fix broken amoor_w rv64uv test
Yunsup Lee
1
-0
/
+3
2013-10-10
revamp hwacha tests
Yunsup Lee
56
-1632
/
+1681
2013-08-23
Reflect changes to ISA
Andrew Waterman
4
-10
/
+10
2013-04-24
cleanup Makefiles in isa
Yunsup Lee
2
-135
/
+34
2013-04-24
add missing RVTEST_CODE_END macros
Yunsup Lee
2
-0
/
+4
2013-04-22
initial commit
Yunsup Lee
64
-0
/
+34364