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Github workflow to run pylint against debug tests
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I'm using this to greatly reduce the timeout when I'm reproducing a
failure I know is going to time out.
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debug: optimize the FreeRtosTest case.
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Add a way to exclude tests by specifying an exclusion file
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This patch adds a way to specify a yaml file which specifies either
for each target individually or for all targets to exclude tests.
Example file format is included in excluded.yaml.example.
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To make sure the rtos module of OpenOCD works well.
Signed-off-by: Chao Du <duchao@eswincomputing.com>
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If the environment variables aren't set, then use the same defaults as
previously.
My current set of tools use riscv64-elf-gcc and riscv64-elf-gdb, and
this makes it trivial to use them.
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- Replace general "Exception" with "GdbServerError" in gdbserver.py for when no
samples are collected
- Replace general "Exception" with "TargetsException" in targets.py for XLEN
mismatch
- Introduce "TestLibError" exception in testlib.py and replace general
exceptions in various locations
- Update pylint.rc to remove overgeneral-exceptions warning
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We were using a variety of deprecated commands.
The driving force behind this was the new way to use `expr{}` as the old
way no longer works with mainline OpenOCD.
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Don't build with -DMULTICORE because this is not a test that really does
multicore. It's one where we just want to park the other harts.
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debug: fix pylint error W0621 redefined-outer-name
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Need to set the etrigger on the hart we're running the test against.
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Test that we work correctly when the hart we're debugging ceases to
respond while it's running.
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Test that we work correctly when the hart we're debugging ceases to
respond during stepi.
Add wait parameter to Gdb.stepi(), in case stepi isn't expected to complete.
Parse "could not read registers" error from gdb
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Confirm basic debug still works when other harts have been parked using
a `cease` instruction. Check that the unavailable harts are inaccessible
from gdb.
Add Gdb.expect()
Parse "unknown thread" error from gdb.
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Also make the semi-hosting test program return 10. That's more fragile
than returning 0, so makes for a better test.
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This gives you less noise in the log, and more chance of figuring out
what code was actually executed.
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`flush regs` is being deprecated.
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`cease` is not a standard RISC-V extension, but is (was?) implemented in
Rocket, and also exists in some SiFive cores. It's useful to test
OpenOCD behavior when a hart becomes unavailable.
See also https://github.com/chipsalliance/rocket-chip/issues/1868
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Also change the test itself to require less RAM than it did previously.
(It had required more than 32KB.)
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It would fail intermittently. We can't guarantee all harts resume
simultaneously. When we let multiple harts run to a breakpoint at the
end of the same loop, one is likely to get there first, and the second
won't make it.
To avoid this problem, run for a short amount of time instead of to a
breakpoint.
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Before it might fail incorrectly, because main was close to trap_entry.
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* Specify trigger type=2 in trigger.S
Previous tests implicitly assume triggers only support type=2. However,
a trigger may support multiple types, i.e., type=15. This commit
explicitly specifies type=2 in trigger.S to support type 15.
* Update debug/programs/trigger.S
Co-authored-by: Tim Newsome <tim@sifive.com>
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
Co-authored-by: Tim Newsome <tim@sifive.com>
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Between October 13 and October 19, something happened that makes the
multi-spike tests 4 times slower. Rolling back spike, OpenOCD, or
riscv-tests doesn't affect this. Presumably it's due to a kernel or
python change in my Ubuntu system.
I don't have time to look at this right now, so just increase the timeouts. :-(
If I had to guess, there could be a bug in rbb_daisychain.py that wastes
a lot of time.
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https://github.com/riscv-software-src/riscv-isa-sim/pull/889 put a UART
at the address we were using in our 32-bit debug tests.
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Fix long line to make pylint happy.
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Using the new spike support merged in
https://github.com/riscv-software-src/riscv-isa-sim/pull/1109
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Not as useful as I'd like because we don't connect until after examine()
has completed, and the test is likely to time out while debugging. But
good to have, and maybe I'll expand on it one day.
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update gdbserver.py; tolerance value of MemorySampleTest()
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The control sequences (^[[?2004h and ^[[?2004l) occur after the
gdb.command, which results in Exception fault. This commit removes the
control sequences and strips out the blank lines (^M).
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These can change at any time and that is OK.
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I don't have time to fix the bug right now, and nobody has run into the
bug yet in any case.
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Turn semihosting_fileio on for every hart. This test still fails if it
ends up running on hart 1 instead of 0, but at least it's closer to
passing. Feels like the remaining problem is in OpenOCD.
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* Another pylint upgrade.
Lots of format string changes, which are more readable.
More files to come...
* Satisfy pylint for two more files.
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