riscv-tools/riscv-tests.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2017-08-28	Make pylint happy.	Tim Newsome	1	-1/+1

2017-08-28	WIP multicore testing.	Tim Newsome	2	-0/+4

2017-08-28	Make the debug tests aware of multicore.	Tim Newsome	5	-13/+28
	Targets now contain an array of harts. When running a regular test, one hart is selected to run the test on while the remaining harts are parked in a safe infinite loop. There's currently only one test that tests multicore behavior, but there could be more. The infrastructure should be able to support heterogeneous multicore, but I don't have a target like that to test with.
2017-08-10	Give these sim targets a chance of passing.	Tim Newsome	2	-3/+7
	Also make sure vsim.log makes it into the generated log file.
2017-06-26	Move target definition into individual files.	Tim Newsome	9	-0/+158
	Instead of defining each target in targets.py, now each target gets its own .py file. This means people can easily keep their own target files around that they may not want to put into the main test source. As part of that, I removed the freedom-u500-sim target since I assume it's only used internally at SiFive. Added a few cleanups as well: * Update README examples, mostly --sim_cmd instead of --cmd. * Allow defining misa in a target, to skip running of ExamineTarget. * Rename target.target() to target.create(), which is less confusing. * Default --sim_cmd to `spike` * Got rid of `use_fpu`, instead looking at F or D in $misa.