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2024-03-01Merge pull request #531 from aap-sc/aap-sc/improvementsEvgeniy Naydanov1-0/+9
improvements to debug tests infrastructure to help with triaging process
2024-02-01[debug tests] print selected seed for PRNGParshintsev Anatoly1-0/+9
Previously the seed was not printed and this created problems with reproduction of the issues. It's still not an ideal - meaning interactions between spike/gdb/openocd are inherently non-determistic (since time is involved), but at least we should get the same sources for the same seed now.
2024-01-23Disable mmu after test translateliangzhen1-0/+4
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-10-24Support instruction count limit in IcountTestliangzhen1-2/+6
This is taking into account that the hardware limits count to 1. Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-10-17Merge pull request #513 from lz-bro/nonexist_csrTim Newsome1-4/+5
Make the non-existent csr configurable
2023-10-17Merge pull request #514 from lz-bro/timer_configurableTim Newsome1-3/+3
Make CLINT address configurable
2023-10-17Make the non-existent csr configurableliangzhen1-4/+5
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-10-16Make CLINT address configurableliangzhen1-3/+3
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-10-13debug: Add UnavailableHaltedTestTim Newsome1-0/+61
Test behavior when a hart becomes unavailable while halted.
2023-10-11Merge pull request #503 from lz-bro/dis_timerTim Newsome1-0/+6
Disable timer interrupt to fix some bugs
2023-10-10Disable timer interrupt to fix some bugsliangzhen1-0/+6
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-09-29debug: Add Openocd.set_available()Tim Newsome1-7/+6
This helper uses dmi_write commands to mark harts available/unavailable.
2023-07-24debug: Re-enable unavailable tests.Tim Newsome1-9/+6
2023-07-19debug: Better comment the privilege tests.Tim Newsome1-3/+4
Just doing this to make a change in the debug files, which should now cause the pylint workflow to execute.
2023-07-18debug: Disable unavailable tests.Tim Newsome1-6/+9
They have issues when run in a github workflow.
2023-07-17Merge pull request #489 from riscv-software-src/power_danceTim Newsome1-13/+59
debug: Test OpenOCD behavior when harts become unavailable, using new spike mechanism
2023-07-17debug: Create UnavailableCycleTestTim Newsome1-0/+27
Use new spike mechanism to test OpenOCD behavior when a hart becomes unavailable, and then available again.
2023-07-17debug: CeaseRunTest -> UnavailableRunTestTim Newsome1-3/+18
Use new spike mechanism to test OpenOCD behavior when the current hart becomes unavailable while running. Create ThreadTerminated exception.
2023-07-17debug: CeaseMultiTest -> UnavailableMultiTestTim Newsome1-6/+13
Use the new spike mechanism to test OpenOCD behavior when a hart becomes unavailable while running. Create CommandException.
2023-07-17parkOtherHarts() already defaults to ceaseTim Newsome1-1/+1
2023-07-17Move "monitor targets" calls into a central place.Tim Newsome1-3/+0
2023-07-13debug: flushregs -> maintenance flush register-cacheTim Newsome1-4/+4
flushregs is deprecated.
2023-07-10Merge pull request #486 from en-sc/en-sc/warning-repeat-readTim Newsome1-2/+15
change warning check in RepeatReadTest
2023-07-07change warning check in RepeatReadTestEvgeniy Naydanov1-2/+15
2023-06-29debug: pylint fix.Tim Newsome1-2/+2
2023-06-15debug: optimize the FreeRtosTest case.Chao Du1-4/+16
To make sure the rtos module of OpenOCD works well. Signed-off-by: Chao Du <duchao@eswincomputing.com>
2023-05-25debug: New pylint => new warnings => new cleanupsTim Newsome1-13/+16
- Replace general "Exception" with "GdbServerError" in gdbserver.py for when no samples are collected - Replace general "Exception" with "TargetsException" in targets.py for XLEN mismatch - Introduce "TestLibError" exception in testlib.py and replace general exceptions in various locations - Update pylint.rc to remove overgeneral-exceptions warning
2023-03-01Fix intermittent IcountTest failure on multi hart.Tim Newsome1-1/+1
Don't build with -DMULTICORE because this is not a test that really does multicore. It's one where we just want to park the other harts.
2023-02-16Add test for icount triggers.Tim Newsome1-0/+27
2023-02-02Fix EtriggerTest on multi-hart targets.Tim Newsome1-0/+1
Need to set the etrigger on the hart we're running the test against.
2023-01-06debug: Add Itrigger test.Tim Newsome1-0/+26
2022-12-29debug: Add etrigger test.Tim Newsome1-0/+19
2022-12-14debug: Add CeaseRunTestTim Newsome1-0/+23
Test that we work correctly when the hart we're debugging ceases to respond while it's running.
2022-12-14debug: Add CeaseStepiTest.Tim Newsome1-0/+23
Test that we work correctly when the hart we're debugging ceases to respond during stepi. Add wait parameter to Gdb.stepi(), in case stepi isn't expected to complete. Parse "could not read registers" error from gdb
2022-12-14debug: Create CeaseMultiTest. (#436)Tim Newsome1-1/+46
Confirm basic debug still works when other harts have been parked using a `cease` instruction. Check that the unavailable harts are inaccessible from gdb. Add Gdb.expect() Parse "unknown thread" error from gdb.
2022-12-14debug: Remove unnecessary exit() functions. (#437)Tim Newsome1-11/+1
Also make the semi-hosting test program return 10. That's more fragile than returning 0, so makes for a better test.
2022-12-01Share exit() among more tests. (#433)Tim Newsome1-15/+0
2022-11-10SvNNTest needs 32KB of RAM. (#428)Tim Newsome1-3/+6
Also change the test itself to require less RAM than it did previously. (It had required more than 32KB.)
2022-11-04Make MulticoreRegTest work with real hardware.Tim Newsome1-16/+18
It would fail intermittently. We can't guarantee all harts resume simultaneously. When we let multiple harts run to a breakpoint at the end of the same loop, one is likely to get there first, and the second won't make it. To avoid this problem, run for a short amount of time instead of to a breakpoint.
2022-11-03Fix PrivChange test address comparison. (#427)Tim Newsome1-3/+4
Before it might fail incorrectly, because main was close to trap_entry.
2022-10-05update gdbserver.py; release tolerance value of MemorySampleTest()YenHaoChen1-2/+2
2022-07-25Ignore `mip` and `time` in DisconnectTest. (#406)Tim Newsome1-1/+2
These can change at any time and that is OK.
2022-07-14Pylint fix. (#405)Tim Newsome1-1/+2
2022-07-14Only run SemihostingFileio on single hart systems. (#404)Tim Newsome1-0/+11
I don't have time to fix the bug right now, and nobody has run into the bug yet in any case.
2022-07-11Debug MemorySampleMixed: Disable 64-bit sampling on 32-bit targets (#402)Luke Wren1-2/+6
2022-07-08Fix SemihostingFileio (#403)Tim Newsome1-1/+2
Turn semihosting_fileio on for every hart. This test still fails if it ends up running on hart 1 instead of 0, but at least it's closer to passing. Feels like the remaining problem is in OpenOCD.
2022-07-01Complete this pass of pylint changes. (#401)Tim Newsome1-142/+144
2022-06-08Test semihosting_fileioTim Newsome1-3/+24
In the original test, confirm that stdout data ends up in the OpenOCD log. In the new test, with `arm semihosting_fileio` enabled, confirm that stdout data ends up in gdb's CLI. This test requires https://github.com/riscv/riscv-openocd/pull/699.
2022-05-31Address pylint warnings. (#385)Tim Newsome1-2/+2
I'm running a newer version of pylint, and thus there are new warnings to be fixed. All very minor.
2022-04-25Add EbreakTest. (#380)Tim Newsome1-0/+31
* Add EbreakTest. Confirm correct behavior when somebody bakes an ebreak instruction into their code. * Forgot to commit ebreak.c
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