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2018-09-04debug: Add first cut to call compliance testscompliance_testsMegan Wachs1-0/+26
2018-08-29Add test case for `riscv expose_custom`.Tim Newsome1-0/+30
Only works against spike, where I've implemented some custom debug registers to test against.
2018-08-27Neuter TriggerStoreAddressInstantTim Newsome1-1/+13
Now that OpenOCD can tell gdb exactly which watchpoint was hit, this test exposes another problem: https://github.com/riscv/riscv-openocd/issues/295 For now neuter the test so the testsuite can still be useful.
2018-08-27Make pylint happy.Tim Newsome1-1/+2
2018-08-25Temporarily disabling PrivChange testAndrew Waterman1-22/+23
@timsifive we are debugging intermittent failures.
2018-08-23Make pylint happy with change d1d2d953b5016b465.Tim Newsome1-2/+3
2018-08-23Merge pull request #153 from dmitryryzhov/rtos-switch-active-threadTim Newsome1-0/+28
Add debug test, which checks that openocd correctly switch active thread on any hart halt.
2018-08-22Disable MulticoreRunHaltStepiTestTim Newsome1-52/+52
It's failing (intermittently?). See eg. https://travis-ci.org/riscv/riscv-tools/builds/418928412?utm_source=github_status&utm_medium=notification
2018-08-22Add debug test, which checks that openocd correctly switch active thread on ↵Dmitry Ryzhov1-0/+28
any hart halt.
2018-08-13Add jump/hbreak test.Tim Newsome1-0/+23
2018-07-03rwatch/watch on explicit addressTim Newsome1-2/+4
Newer gdb requires more debug info in order to "watch data" in this test. I'm not sure how to make that debug info happen, so instead we tell it the address to use.
2018-05-18Fix MulticoreRunHaltStepiTestTim Newsome1-19/+37
The test actually wasn't checking interrupt counts at all. Fixing it required some other changes: Make sure all harts get to run Add some retries, since on a loaded machine against spike both harts might not get to run, even if you give spike a generous amount of time to do so.
2018-05-14Merge remote-tracking branch 'origin/downloadtest' into debug-tests-more-singleMegan Wachs1-17/+4
2018-05-14Make DownloadTest properly park other harts.Tim Newsome1-1/+2
2018-05-14debug: remove some unintentionally added newlinesMegan Wachs1-2/+0
2018-05-14debug: Fixing the non-RTOS behavior for DownloadTestMegan Wachs1-7/+16
2018-05-11debug: mark more tests as single-hart testsMegan Wachs1-6/+13
2018-04-30Fix formatting to make pylint happy.Tim Newsome1-5/+6
2018-04-27debug: need to clear satp before changing privdebug-clear-satpMegan Wachs1-0/+7
ISA Manual does not require this register to be reset, and attempting to execute code with VM on when VM hasn't been set up is going to just lead to sadness.
2018-04-09Compute gdb command timeout based on ops estimateTim Newsome1-1/+1
The caller of gdb.command() should estimate how much work gdb needs to do, and testlib then scales this up proportional to the general gdb timeout we configured. This hopefully allows us to configure a tighter timeout, so we don't have to have a multi-hour timeout just for something that takes long like `load` on a really slow simulator. Hopefully this addresses #122.
2018-03-01Ensure an error when reading a non-existent CSR.Tim Newsome1-0/+13
2018-02-09Test resuming from a trigger.resume_from_triggerTim Newsome1-0/+5
2018-01-08Deal with gdb reporting pmpcfg0 not existing.Tim Newsome1-3/+7
It's an optional register.
2018-01-05Add test for multicore failureTim Newsome1-0/+28
Specifically, make sure that after resuming all cores, and halting core 0, that OpenOCD's poll() doesn't mess up the currently selected hart to the point where memory accesses intended for core 0 go to core 1.
2017-12-27Test FPRs that aren't XLEN in size.Tim Newsome1-0/+6
Cover all combinations of 32,64 bit XLEN with F and FD extensions. Finishes Issue https://github.com/riscv/riscv-openocd/issues/110
2017-12-20Verify that F18 does not exist on FPU-less targetsTim Newsome1-17/+20
2017-12-01Ensure there are no unnamed registers.Tim Newsome1-0/+2
2017-11-19Make pylint happy.Tim Newsome1-1/+2
2017-11-16Debug: Use the --32 and --64 command line arguments (#97)Megan Wachs1-4/+0
* Debug: Actually use the --32 and --64 command line arguments * debug: make XLEN mismatch message clearer
2017-11-16Disable PMP for PrivRw test.Tim Newsome1-0/+5
2017-11-15Clarify PrivTest detail.Tim Newsome1-0/+2
2017-11-02Add --print-log-names to print temp log names ASAPTim Newsome1-0/+2
When not passed, they are no longer printed out.
2017-11-01Make pylint 1.6.5 happy.Tim Newsome1-1/+1
2017-11-01Test register aliases in the simple register testsTim Newsome1-9/+17
2017-11-01Fix MulticoreRegTest.Tim Newsome1-58/+54
This test would fail intermittently if gdb on the first hart managed to set a breakpoint, resume, halt, and clear the breakpoint before the second hart got a chance to resume.
2017-10-31Temporarily comment out MulticoreRegTest due to flakiness.Richard Xia1-57/+58
2017-10-19Get helpful gdb output in MemTestBlock.Tim Newsome1-1/+4
2017-10-04Resurrect priv tests.Tim Newsome1-52/+51
2017-09-29Fix tests to work in multi-gdb mode.Tim Newsome1-12/+17
The Gdb class now can handle connecting to more than one gdb. It enumerates the harts across all connections, and when asked to select a hart, it transparently sends future gdb commands to the correct instance. Multicore tests still have to be aware of some differences. The main one is that when executing 'c' in RTOS mode, all harts resume, while in multi-gdb mode only the current one resumes. Additionally, gdb doesn't set breakpoints until 'c' is issued, so the hart where breakpoints are set needs to be resumed before other harts might see them.
2017-09-19Allow multiple reset vectors.Tim Newsome1-1/+1
Some boards have jumpers that control the reset vector, and forcing them one way or another is more annoying than dealing with it in software.
2017-09-18Add interrupts to MulticoreRunHaltStepiTest.Tim Newsome1-1/+8
Just to hammer on anything at once, and hopefully catch weird interactions if they exist.
2017-09-14Test debugging code with interrupts.Tim Newsome1-0/+43
2017-09-01Add some infrastructure for multicore tests.Tim Newsome1-1/+1
When compiling, define the number of harts. This means we only need to allocate a lot of stack if there are a lot of harts.
2017-08-28Make MemTestBlock output a more descriptive error.Tim Newsome1-11/+15
2017-08-28Fix MemTest* after sloppy rebase.Tim Newsome1-2/+2
2017-08-28Rename test to MulticoreRunHaltStepiTest.Tim Newsome1-1/+1
2017-08-28WIP multicore testing.Tim Newsome1-5/+31
2017-08-28Make the debug tests aware of multicore.Tim Newsome1-46/+47
Targets now contain an array of harts. When running a regular test, one hart is selected to run the test on while the remaining harts are parked in a safe infinite loop. There's currently only one test that tests multicore behavior, but there could be more. The infrastructure should be able to support heterogeneous multicore, but I don't have a target like that to test with.
2017-08-28Increase delay in UserInterrupt.Tim Newsome1-1/+1
When a machine is very loaded, otherwise it could happen that we send the interrupt before the resume has actually happened.
2017-08-13Make MemTest* catch reading too many words.Tim Newsome1-7/+6
For one of the test addresses, use the highest possible one to ensure that OpenOCD isn't secretly reading/writing more words than requested.
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