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2023-05-01Update OpenOCD cfg files to new syntaxTim Newsome7-34/+34
2023-04-06Augment LR/SC test to test that SC-after-failed-SC failsAndrew Waterman1-2/+5
2023-04-06Merge pull request #466 from riscv-software-src/spike-zicntrAndrew Waterman1-2/+2
2023-04-06Merge pull request #464 from nervosnetwork/amocmp_wAndrew Waterman4-1/+40
2023-04-06Include Zicntr in Spike ISA stringAndrew Waterman1-2/+2
2023-04-06Add more tests for amomax/maxu/min/minu_wmohanson4-1/+40
2023-03-16Bump env to cope with Smrnmi extensionAndrew Waterman1-0/+0
2023-03-16Fix breakpoint.S failing when tcontrol is implemented (#463)Luke Wren1-0/+10
2023-03-03bump envAndrew Waterman1-0/+0
2023-03-02Merge pull request #461 from riscv-software-src/icount_fixTim Newsome1-1/+1
2023-03-01Fix intermittent IcountTest failure on multi hart.Tim Newsome1-1/+1
2023-02-28Merge pull request #458 from Du-Chao/masterTim Newsome1-2/+2
2023-02-28Merge pull request #456 from riscv-software-src/icountTim Newsome1-0/+27
2023-02-27rv32ui test misaligned load/store data (#459)Jesse Taube3-5/+9
2023-02-21debug: fix pylint error W0621 redefined-outer-nameChao Du1-2/+2
2023-02-16Add test for icount triggers.Tim Newsome1-0/+27
2023-02-15Merge pull request #451 from riscv-software-src/etrigger_fixTim Newsome1-0/+1
2023-02-13Fix ma_fetch test for norvc (#454)Yujia Qiao1-1/+1
2023-02-13Update register name to satp (#455)Pascal Cotret1-1/+1
2023-02-03env: update commit hash for submodule env (#452)deepak04141-0/+0
2023-02-02Fix EtriggerTest on multi-hart targets.Tim Newsome1-0/+1
2023-01-19Fix ma_fetch test for writable misa.C (#449)Jerry Zhao1-3/+3
2023-01-19Pass --misaligned flag to Spike to run ISA tests (#445)Andrew Waterman1-2/+2
2023-01-06Merge pull request #446 from riscv-software-src/itriggerTim Newsome2-1/+30
2023-01-06debug: Add Itrigger test.Tim Newsome1-0/+26
2023-01-06debug: Tweak interrupt.c, so a test can run to exit()Tim Newsome1-1/+4
2023-01-06Merge pull request #447 from riscv-software-src/etriggerTim Newsome2-1/+20
2022-12-29Merge branch 'jerryz123-fix-ma_fetch'Andrew Waterman1-9/+31
2022-12-29debug: Add etrigger test.Tim Newsome2-1/+20
2022-12-28Fix ma_fetch test to support systems where no RVC does not imply IALIGN=32Jerry Zhao1-9/+31
2022-12-28Fix clean in isa/ with non-default compiler (#443)Alex Shpilkin1-1/+1
2022-12-27Merge pull request #442 from riscv-software-src/ceasetestTim Newsome2-3/+60
2022-12-14debug: Add CeaseRunTestTim Newsome1-0/+23
2022-12-14debug: Add CeaseStepiTest.Tim Newsome2-3/+37
2022-12-14debug: Create CeaseMultiTest. (#436)Tim Newsome2-2/+55
2022-12-14debug: Remove unnecessary exit() functions. (#437)Tim Newsome3-11/+4
2022-12-08Fix regression in VcsSim introduced by #334 (#440)Jerry Zhao1-0/+1
2022-12-07zicntr: separate cycle/instret accessibility test (#439)Chih-Min Chao5-16/+69
2022-12-01debug: Disassemble memory when a failure happens. (#432)Tim Newsome1-1/+1
2022-12-01`flush regs` -> `maintenance flush register-cache` (#431)Tim Newsome1-1/+1
2022-12-01debug: Park unused harts with a cease instruction. (#434)Tim Newsome3-2/+23
2022-12-01Share exit() among more tests. (#433)Tim Newsome3-16/+9
2022-11-10SvNNTest needs 32KB of RAM. (#428)Tim Newsome2-4/+7
2022-11-04Make MulticoreRegTest work with real hardware.Tim Newsome2-17/+19
2022-11-03Fix PrivChange test address comparison. (#427)Tim Newsome1-3/+4
2022-10-26Specify trigger type=2 in trigger.S (#425)YenHaoChen1-2/+3
2022-10-24Increase timeouts for multi-spike test. (#423)Tim Newsome2-3/+4
2022-10-21Change memory address used in debug tests. (#422)Tim Newsome4-3/+3
2022-10-20Merge pull request #421 from riscv-software-src/pylintTim Newsome1-1/+2
2022-10-20Merge pull request #420 from riscv-software-src/test_fpr_progbufTim Newsome3-2/+9
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