| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2018-04-27 | debug: add missing align directive on trap_entrytrap_entry_align-1 | Megan Wachs | 1 | -0/+1 | |
| 2018-04-24 | Fix race when making logs directory | Tim Newsome | 1 | -1/+5 | |
| 2018-04-16 | Merge pull request #123 from riscv/gdb_timeout | Tim Newsome | 2 | -14/+18 | |
| Compute gdb command timeout based on ops estimate | |||||
| 2018-04-09 | Compute gdb command timeout based on ops estimate | Tim Newsome | 2 | -14/+18 | |
| The caller of gdb.command() should estimate how much work gdb needs to do, and testlib then scales this up proportional to the general gdb timeout we configured. This hopefully allows us to configure a tighter timeout, so we don't have to have a multi-hour timeout just for something that takes long like `load` on a really slow simulator. Hopefully this addresses #122. | |||||
| 2018-04-09 | Fix #120: Instructions 'sll' are replaced with 'slli' in rv64ui/slli.S (#121) | Andrei Tatarnikov | 1 | -3/+3 | |
| 2018-04-02 | Use `gdb_report_register_access_error enable` | Tim Newsome | 4 | -0/+6 | |
| 2018-03-27 | Test debug authentication. | Tim Newsome | 4 | -3/+19 | |
| Also halt instead of reset spike targets, which tests a more complicated code path. | |||||
| 2018-03-23 | Print log filename at the end of the log. | Tim Newsome | 1 | -0/+1 | |
| This makes it much easier to look at a log if you see a failure scrolling by on your terminal. | |||||
| 2018-03-21 | Make misa.C test conform to Hauser proposal | Andrew Waterman | 1 | -43/+10 | |
| See https://github.com/riscv/riscv-isa-manual/commit/0472bcdd166f45712492829a250e228bb45fa5e7 | |||||
| 2018-03-20 | Merge pull request #119 from rishikhan/master | Palmer Dabbelt | 1 | -2/+8 | |
| Update Makefile to allow for RISCV_PREFIX to be set by the configure | |||||
| 2018-03-19 | Update Makefile to allow for RISCV_PREFIX to be set by the configure --target | rishi | 1 | -2/+8 | |
| 2018-03-01 | Test debugging with/without a program buffer | Tim Newsome | 5 | -5/+10 | |
| 2018-03-01 | Ensure an error when reading a non-existent CSR. | Tim Newsome | 5 | -0/+29 | |
| 2018-02-27 | Add test for clearing misa.C while PC is misaligned (#117) | Andrew Waterman | 1 | -1/+79 | |
| See https://github.com/riscv/riscv-isa-manual/pull/139 | |||||
| 2018-02-09 | Test resuming from a trigger.resume_from_trigger | Tim Newsome | 3 | -10/+9 | |
| 2018-02-07 | Link scripts shouldn't be executable. | Tim Newsome | 1 | -0/+0 | |
| 2018-01-08 | Deal with gdb reporting pmpcfg0 not existing. | Tim Newsome | 2 | -3/+16 | |
| It's an optional register. | |||||
| 2018-01-05 | Add test for multicore failure | Tim Newsome | 2 | -5/+40 | |
| Specifically, make sure that after resuming all cores, and halting core 0, that OpenOCD's poll() doesn't mess up the currently selected hart to the point where memory accesses intended for core 0 go to core 1. | |||||
| 2018-01-02 | Test access exception behavior for illegal addresses (#111) | Andrew Waterman | 2 | -0/+71 | |
| OK'd by @palmer-dabbelt | |||||
| 2017-12-27 | Test FPRs that aren't XLEN in size. | Tim Newsome | 6 | -8/+20 | |
| Cover all combinations of 32,64 bit XLEN with F and FD extensions. Finishes Issue https://github.com/riscv/riscv-openocd/issues/110 | |||||
| 2017-12-21 | Add all-tests target. | Tim Newsome | 1 | -1/+3 | |
| I hope to use this in riscv-tools' regression.sh. | |||||
| 2017-12-21 | Merge pull request #110 from riscv/bump_env | Megan Wachs | 1 | -5/+5 | |
| tests: bump env to pick up new names for CSRs | |||||
| 2017-12-21 | tests: bump env to pick up new names for CSRs | Megan Wachs | 1 | -5/+5 | |
| 2017-12-20 | Remove `set arch riscv:rv%d` | Tim Newsome | 1 | -1/+0 | |
| gdb gets target XLEN from register width now, so this is taken care of automatically. | |||||
| 2017-12-20 | Verify that F18 does not exist on FPU-less targets | Tim Newsome | 1 | -17/+20 | |
| 2017-12-12 | Display env variables used when invoking OpenOCD | Tim Newsome | 2 | -6/+11 | |
| This makes it a little easier to just cut and paste from the log when reproducing a failure. (The port number still needs changing though.) | |||||
| 2017-12-01 | Ensure there are no unnamed registers. | Tim Newsome | 1 | -0/+2 | |
| 2017-11-30 | Merge pull request #109 from riscv/vcssim | Tim Newsome | 1 | -2/+12 | |
| Clean up VcsSim init() | |||||
| 2017-11-30 | Clean up VcsSim init() | Tim Newsome | 1 | -2/+12 | |
| Use a unique log file, so you can run multiple instances at once. Add time out to waiting for the simulator to be ready. | |||||
| 2017-11-27 | Rename sbadaddr to satp | Andrew Waterman | 5 | -14/+14 | |
| 2017-11-26 | Rv32ud tests (#108) | Torbjørn | 23 | -0/+318 | |
| * Probably implemented the changes required to support fadd test for rv32ud * Created test files in rv32ud, implemented working(?) test for ldst * fclass, fcvt_w, fmin and recoding seem to be working now * Got fdiv (and sqrt) tests working * fmadd tests seem to work * fcmp works * [WIP] fcvt working, but lacks a 32-bit implementation of the final test * Renamed macro TEST_LDST_D32 to TEST_CASE_D32 to indicate that it can be used for more than just LDST * Added Makefrag for rv32ud tests and included in main isa Makefile * Don't run 64-bit tests if the defined XLEN is 32 | |||||
| 2017-11-22 | Check sepc for rv64si/scall test. (#107) | Christopher Celio | 1 | -0/+4 | |
| Closes #105. | |||||
| 2017-11-20 | Check mtval in rv64mi-p-illegal (#104) | Andrew Waterman | 1 | -0/+11 | |
| Closes #103 | |||||
| 2017-11-19 | Ensure log file is fully written before reading it | Tim Newsome | 1 | -0/+1 | |
| Fixes --print-failures sometimes not actually printing out details about failures. | |||||
| 2017-11-19 | Make pylint happy. | Tim Newsome | 3 | -12/+16 | |
| 2017-11-17 | Merge pull request #102 from riscv/xlen_fix | Megan Wachs | 1 | -7/+8 | |
| debug: Fix the XLEN command line check | |||||
| 2017-11-17 | debug: Fix the XLEN command line checkxlen_fix | Megan Wachs | 1 | -7/+8 | |
| 2017-11-16 | Debug: Use the --32 and --64 command line arguments (#97) | Megan Wachs | 3 | -10/+17 | |
| * Debug: Actually use the --32 and --64 command line arguments * debug: make XLEN mismatch message clearer | |||||
| 2017-11-16 | Disable PMP for PrivRw test. | Tim Newsome | 1 | -0/+5 | |
| 2017-11-15 | Clarify PrivTest detail. | Tim Newsome | 1 | -0/+2 | |
| 2017-11-11 | Make sure that code is 4-byte aligned before disabling rvc (#100) | Andrew Waterman | 4 | -1/+5 | |
| 2017-11-09 | Make rv64mi-p-ecall work when U-mode is not present | Andrew Waterman | 1 | -1/+17 | |
| 2017-11-09 | Use mstatus.MPP to check existence of U-mode | Andrew Waterman | 1 | -5/+6 | |
| misa is allowed to be hardwired to 0, so checking its U bit could incorrectly suggest that U-mode is not supported. | |||||
| 2017-11-02 | Add --print-log-names to print temp log names ASAP | Tim Newsome | 2 | -5/+17 | |
| When not passed, they are no longer printed out. | |||||
| 2017-11-02 | Ensure gdb connection failures end up in main log. | Tim Newsome | 1 | -9/+18 | |
| 2017-11-02 | debug: Need to apply remotetimeout before connecting to remote target (#94) | Megan Wachs | 1 | -6/+7 | |
| * debug: Need to apply remotetimeout before connecting to remote target * debug: whitespace cleanup | |||||
| 2017-11-01 | SBREAK test now checks EPC value. (#92) | Christopher Celio | 1 | -0/+4 | |
| Closes #89 | |||||
| 2017-11-01 | Make pylint 1.6.5 happy. | Tim Newsome | 4 | -6/+5 | |
| 2017-11-01 | Test register aliases in the simple register tests | Tim Newsome | 1 | -9/+17 | |
| 2017-11-01 | Fix MulticoreRegTest. | Tim Newsome | 2 | -59/+65 | |
| This test would fail intermittently if gdb on the first hart managed to set a breakpoint, resume, halt, and clear the breakpoint before the second hart got a chance to resume. | |||||
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index : riscv-tools/riscv-tests.git | |
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