Age | Commit message (Collapse) | Author | Files | Lines | |
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2018-08-25 | Temporarily disabling PrivChange testprivchange-dontdeleteme | Andrew Waterman | 1 | -22/+23 | |
@timsifive we are debugging intermittent failures. | |||||
2018-05-21 | Merge pull request #141 from riscv/mrhstest | Tim Newsome | 2 | -23/+46 | |
Fix MulticoreRunHaltStepiTest | |||||
2018-05-18 | Fix MulticoreRunHaltStepiTest | Tim Newsome | 2 | -23/+46 | |
The test actually wasn't checking interrupt counts at all. Fixing it required some other changes: Make sure all harts get to run Add some retries, since on a loaded machine against spike both harts might not get to run, even if you give spike a generous amount of time to do so. | |||||
2018-05-15 | Merge pull request #139 from riscv/debug-tests-more-single | Megan Wachs | 2 | -10/+19 | |
Mark more Debug tests as "Single Hart" | |||||
2018-05-14 | Merge remote-tracking branch 'origin/downloadtest' into debug-tests-more-single | Megan Wachs | 2 | -21/+11 | |
2018-05-14 | Make DownloadTest properly park other harts. | Tim Newsome | 2 | -5/+9 | |
2018-05-14 | debug: remove some unintentionally added newlines | Megan Wachs | 1 | -2/+0 | |
2018-05-14 | debug: Fixing the non-RTOS behavior for DownloadTest | Megan Wachs | 1 | -7/+16 | |
2018-05-11 | debug: mark more tests as single-hart tests | Megan Wachs | 1 | -6/+13 | |
2018-05-11 | debug: output some more useful info into the post-mortem data | Megan Wachs | 1 | -0/+5 | |
2018-04-30 | [rv64ua/lrsc] Initialize memory read out. (#135) | Christopher Celio | 1 | -1/+3 | |
* [rv64ua/lrsc] Initialize memory read out. Even though the load contents are discarded, this un-initialized memory value can lead to a divergence for co-simulation between two different RISC-V designs. * [rv64ua/lrsc] Use .skip instead of .align. | |||||
2018-04-30 | Fix formatting to make pylint happy. | Tim Newsome | 1 | -5/+6 | |
2018-04-28 | Merge pull request #132 from riscv/debug-clear-satp | Megan Wachs | 1 | -0/+7 | |
debug: need to clear satp before changing priv | |||||
2018-04-27 | debug: need to clear satp before changing privdebug-clear-satp | Megan Wachs | 1 | -0/+7 | |
ISA Manual does not require this register to be reset, and attempting to execute code with VM on when VM hasn't been set up is going to just lead to sadness. | |||||
2018-04-27 | Merge pull request #125 from riscv/debug-delete-sim | Megan Wachs | 1 | -17/+0 | |
Delete E300Sim.py | |||||
2018-04-27 | Merge pull request #130 from riscv/trap_entry_align-1 | Megan Wachs | 1 | -0/+1 | |
debug: add missing align directive on trap_entry | |||||
2018-04-27 | debug: add missing align directive on trap_entrytrap_entry_align-1 | Megan Wachs | 1 | -0/+1 | |
2018-04-24 | Fix race when making logs directory | Tim Newsome | 1 | -1/+5 | |
2018-04-19 | Delete E300Sim.pydebug-delete-sim | Megan Wachs | 1 | -17/+0 | |
This file is wrong (the .cfg file isn't right) and not used by anything. | |||||
2018-04-16 | Merge pull request #123 from riscv/gdb_timeout | Tim Newsome | 2 | -14/+18 | |
Compute gdb command timeout based on ops estimate | |||||
2018-04-09 | Compute gdb command timeout based on ops estimate | Tim Newsome | 2 | -14/+18 | |
The caller of gdb.command() should estimate how much work gdb needs to do, and testlib then scales this up proportional to the general gdb timeout we configured. This hopefully allows us to configure a tighter timeout, so we don't have to have a multi-hour timeout just for something that takes long like `load` on a really slow simulator. Hopefully this addresses #122. | |||||
2018-04-09 | Fix #120: Instructions 'sll' are replaced with 'slli' in rv64ui/slli.S (#121) | Andrei Tatarnikov | 1 | -3/+3 | |
2018-04-02 | Use `gdb_report_register_access_error enable` | Tim Newsome | 4 | -0/+6 | |
2018-03-27 | Test debug authentication. | Tim Newsome | 4 | -3/+19 | |
Also halt instead of reset spike targets, which tests a more complicated code path. | |||||
2018-03-23 | Print log filename at the end of the log. | Tim Newsome | 1 | -0/+1 | |
This makes it much easier to look at a log if you see a failure scrolling by on your terminal. | |||||
2018-03-21 | Make misa.C test conform to Hauser proposal | Andrew Waterman | 1 | -43/+10 | |
See https://github.com/riscv/riscv-isa-manual/commit/0472bcdd166f45712492829a250e228bb45fa5e7 | |||||
2018-03-20 | Merge pull request #119 from rishikhan/master | Palmer Dabbelt | 1 | -2/+8 | |
Update Makefile to allow for RISCV_PREFIX to be set by the configure | |||||
2018-03-19 | Update Makefile to allow for RISCV_PREFIX to be set by the configure --target | rishi | 1 | -2/+8 | |
2018-03-01 | Test debugging with/without a program buffer | Tim Newsome | 5 | -5/+10 | |
2018-03-01 | Ensure an error when reading a non-existent CSR. | Tim Newsome | 5 | -0/+29 | |
2018-02-27 | Add test for clearing misa.C while PC is misaligned (#117) | Andrew Waterman | 1 | -1/+79 | |
See https://github.com/riscv/riscv-isa-manual/pull/139 | |||||
2018-02-09 | Test resuming from a trigger.resume_from_trigger | Tim Newsome | 3 | -10/+9 | |
2018-02-07 | Link scripts shouldn't be executable. | Tim Newsome | 1 | -0/+0 | |
2018-01-08 | Deal with gdb reporting pmpcfg0 not existing. | Tim Newsome | 2 | -3/+16 | |
It's an optional register. | |||||
2018-01-05 | Add test for multicore failure | Tim Newsome | 2 | -5/+40 | |
Specifically, make sure that after resuming all cores, and halting core 0, that OpenOCD's poll() doesn't mess up the currently selected hart to the point where memory accesses intended for core 0 go to core 1. | |||||
2018-01-02 | Test access exception behavior for illegal addresses (#111) | Andrew Waterman | 2 | -0/+71 | |
OK'd by @palmer-dabbelt | |||||
2017-12-27 | Test FPRs that aren't XLEN in size. | Tim Newsome | 6 | -8/+20 | |
Cover all combinations of 32,64 bit XLEN with F and FD extensions. Finishes Issue https://github.com/riscv/riscv-openocd/issues/110 | |||||
2017-12-21 | Add all-tests target. | Tim Newsome | 1 | -1/+3 | |
I hope to use this in riscv-tools' regression.sh. | |||||
2017-12-21 | Merge pull request #110 from riscv/bump_env | Megan Wachs | 1 | -5/+5 | |
tests: bump env to pick up new names for CSRs | |||||
2017-12-21 | tests: bump env to pick up new names for CSRs | Megan Wachs | 1 | -5/+5 | |
2017-12-20 | Remove `set arch riscv:rv%d` | Tim Newsome | 1 | -1/+0 | |
gdb gets target XLEN from register width now, so this is taken care of automatically. | |||||
2017-12-20 | Verify that F18 does not exist on FPU-less targets | Tim Newsome | 1 | -17/+20 | |
2017-12-12 | Display env variables used when invoking OpenOCD | Tim Newsome | 2 | -6/+11 | |
This makes it a little easier to just cut and paste from the log when reproducing a failure. (The port number still needs changing though.) | |||||
2017-12-01 | Ensure there are no unnamed registers. | Tim Newsome | 1 | -0/+2 | |
2017-11-30 | Merge pull request #109 from riscv/vcssim | Tim Newsome | 1 | -2/+12 | |
Clean up VcsSim init() | |||||
2017-11-30 | Clean up VcsSim init() | Tim Newsome | 1 | -2/+12 | |
Use a unique log file, so you can run multiple instances at once. Add time out to waiting for the simulator to be ready. | |||||
2017-11-27 | Rename sbadaddr to satp | Andrew Waterman | 5 | -14/+14 | |
2017-11-26 | Rv32ud tests (#108) | Torbjørn | 23 | -0/+318 | |
* Probably implemented the changes required to support fadd test for rv32ud * Created test files in rv32ud, implemented working(?) test for ldst * fclass, fcvt_w, fmin and recoding seem to be working now * Got fdiv (and sqrt) tests working * fmadd tests seem to work * fcmp works * [WIP] fcvt working, but lacks a 32-bit implementation of the final test * Renamed macro TEST_LDST_D32 to TEST_CASE_D32 to indicate that it can be used for more than just LDST * Added Makefrag for rv32ud tests and included in main isa Makefile * Don't run 64-bit tests if the defined XLEN is 32 | |||||
2017-11-22 | Check sepc for rv64si/scall test. (#107) | Christopher Celio | 1 | -0/+4 | |
Closes #105. | |||||
2017-11-20 | Check mtval in rv64mi-p-illegal (#104) | Andrew Waterman | 1 | -0/+11 | |
Closes #103 |