| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2017-11-01 | SBREAK test now checks EPC value. (#92) | Christopher Celio | 1 | -0/+4 | |
| Closes #89 | |||||
| 2017-11-01 | Make pylint 1.6.5 happy. | Tim Newsome | 4 | -6/+5 | |
| 2017-11-01 | Test register aliases in the simple register tests | Tim Newsome | 1 | -9/+17 | |
| 2017-11-01 | Fix MulticoreRegTest. | Tim Newsome | 2 | -59/+65 | |
| This test would fail intermittently if gdb on the first hart managed to set a breakpoint, resume, halt, and clear the breakpoint before the second hart got a chance to resume. | |||||
| 2017-10-31 | Merge pull request #90 from richardxia/comment-out-multicore-reg-test | Palmer Dabbelt | 1 | -57/+58 | |
| Temporarily comment out MulticoreRegTest due to flakiness. | |||||
| 2017-10-31 | Temporarily comment out MulticoreRegTest due to flakiness. | Richard Xia | 1 | -57/+58 | |
| 2017-10-30 | Remove cache miss test from last AMO test. (#88) | Richard Xia | 1 | -17/+0 | |
| Follow-up to b68b39031a730ecc155ed87fba2ed5f111d0ab07. The 64KiB allocated by the code to force a cache miss makes it impossible to run the test from any memories that are smaller 64KiB, such as scratchpad memories or LIMs. Since this is trying to test microarchitectural behavior, they don't belong in these ISA tests anyway. | |||||
| 2017-10-30 | Declare trap handlers as global symbols. (#87) | Richard Xia | 8 | -0/+9 | |
| This allows them to be referenced by other files, such as a test environment that lives in a separate compilation unit. | |||||
| 2017-10-26 | Verify that mtval/stval is written correctly on misaligned fetch | Andrew Waterman | 1 | -1/+9 | |
| 2017-10-26 | Fix rv64mi-csr for the case where U-mode is not available. (#86) | Richard Xia | 1 | -0/+16 | |
| 2017-10-24 | Increase dual-core RV64 timeouts. | Tim Newsome | 2 | -2/+2 | |
| I need this for CompareSections to pass when I instrument spike to be really slow. | |||||
| 2017-10-19 | Get helpful gdb output in MemTestBlock. | Tim Newsome | 1 | -1/+4 | |
| 2017-10-12 | Pay attention to server_timeout_sec | Tim Newsome | 1 | -2/+3 | |
| Fixes #83. | |||||
| 2017-10-04 | Resurrect priv tests. | Tim Newsome | 1 | -52/+51 | |
| 2017-10-04 | Merge pull request #79 from riscv/multigdb | Tim Newsome | 13 | -96/+236 | |
| Multigdb support | |||||
| 2017-09-29 | Make ExamineTarget multi-core aware. | Tim Newsome | 1 | -18/+23 | |
| Now on multi-core targets it only runs once, wasting less time. | |||||
| 2017-09-29 | Fix tests to work in multi-gdb mode. | Tim Newsome | 13 | -87/+236 | |
| The Gdb class now can handle connecting to more than one gdb. It enumerates the harts across all connections, and when asked to select a hart, it transparently sends future gdb commands to the correct instance. Multicore tests still have to be aware of some differences. The main one is that when executing 'c' in RTOS mode, all harts resume, while in multi-gdb mode only the current one resumes. Additionally, gdb doesn't set breakpoints until 'c' is issued, so the hart where breakpoints are set needs to be resumed before other harts might see them. | |||||
| 2017-09-22 | Remove unused function. | Tim Newsome | 1 | -9/+0 | |
| 2017-09-21 | Add coverage for single-core non-rtos OpenOCD. | Tim Newsome | 4 | -3/+19 | |
| 2017-09-19 | Allow multiple reset vectors. | Tim Newsome | 4 | -3/+8 | |
| Some boards have jumpers that control the reset vector, and forcing them one way or another is more annoying than dealing with it in software. | |||||
| 2017-09-19 | Link against libm for fma() | Andrew Waterman | 1 | -1/+1 | |
| 2017-09-19 | Merge pull request #76 from riscv/multicore | Tim Newsome | 3 | -14/+28 | |
| Add interrupts to MulticoreRunHaltStepiTest. | |||||
| 2017-09-19 | Forgot to commit this earlier. | Tim Newsome | 1 | -0/+20 | |
| Fixes #77. | |||||
| 2017-09-18 | Add interrupts to MulticoreRunHaltStepiTest. | Tim Newsome | 4 | -16/+29 | |
| Just to hammer on anything at once, and hopefully catch weird interactions if they exist. | |||||
| 2017-09-15 | Don't read entire log into RAM just to print it. | Tim Newsome | 1 | -2/+1 | |
| 2017-09-14 | misa is stored in the hart now, not the target | Tim Newsome | 1 | -6/+6 | |
| 2017-09-14 | When spike fails to launch, display its output. | Tim Newsome | 1 | -21/+29 | |
| 2017-09-14 | Test debugging code with interrupts. | Tim Newsome | 5 | -4/+80 | |
| 2017-09-14 | Call postMortem() when a test fails. | Tim Newsome | 2 | -8/+15 | |
| 2017-09-14 | Clarify timeout units. | Tim Newsome | 1 | -0/+1 | |
| 2017-09-14 | Move link options to end of gcc command line | Andrew Waterman | 1 | -1/+1 | |
| 2017-09-12 | Merge pull request #69 from riscv/multicore | Tim Newsome | 23 | -209/+486 | |
| Proper multicore support for debug tests | |||||
| 2017-09-01 | Improve ma_fetch test to cover JAL and branches | Andrew Waterman | 1 | -1/+48 | |
| 2017-09-01 | Add some infrastructure for multicore tests. | Tim Newsome | 5 | -40/+61 | |
| When compiling, define the number of harts. This means we only need to allocate a lot of stack if there are a lot of harts. | |||||
| 2017-09-01 | Use 32-bit link script for 32-bit target. | Tim Newsome | 1 | -1/+1 | |
| 2017-08-28 | This file isn't ready yet. | Tim Newsome | 1 | -11/+0 | |
| 2017-08-28 | Forgot to add this file. | Tim Newsome | 1 | -0/+81 | |
| 2017-08-28 | Increase remotetimeout for spike targets. | Tim Newsome | 5 | -0/+15 | |
| On overloaded systems, when executing compare-sections, otherwise gdb might hit a timeout and the compare-sections code doesn't deal with it. (You get an error message complaining that 130 is not a valid hex digit.) | |||||
| 2017-08-28 | Fix rebase bug. | Tim Newsome | 1 | -1/+3 | |
| 2017-08-28 | Make MemTestBlock output a more descriptive error. | Tim Newsome | 1 | -11/+15 | |
| 2017-08-28 | Fix MemTest* after sloppy rebase. | Tim Newsome | 1 | -2/+2 | |
| 2017-08-28 | Rename test to MulticoreRunHaltStepiTest. | Tim Newsome | 1 | -1/+1 | |
| 2017-08-28 | Make pylint happy. | Tim Newsome | 3 | -3/+3 | |
| 2017-08-28 | WIP multicore testing. | Tim Newsome | 7 | -18/+95 | |
| 2017-08-28 | WIP towards multiple gdb instances. | Tim Newsome | 1 | -4/+14 | |
| 2017-08-28 | Make the debug tests aware of multicore. | Tim Newsome | 17 | -189/+267 | |
| Targets now contain an array of harts. When running a regular test, one hart is selected to run the test on while the remaining harts are parked in a safe infinite loop. There's currently only one test that tests multicore behavior, but there could be more. The infrastructure should be able to support heterogeneous multicore, but I don't have a target like that to test with. | |||||
| 2017-08-28 | Increase delay in UserInterrupt. | Tim Newsome | 1 | -1/+1 | |
| When a machine is very loaded, otherwise it could happen that we send the interrupt before the resume has actually happened. | |||||
| 2017-08-16 | Merge pull request #67 from riscv/sfence_vma | Palmer Dabbelt | 2 | -6/+9 | |
| Inform GCC that "sfence.vma" clobbers memory | |||||
| 2017-08-16 | Inform GCC that "sfence.vma" clobbers memory | Palmer Dabbelt | 2 | -6/+9 | |
| 2017-08-14 | Put logfile code back so everything works again. | Tim Newsome | 2 | -4/+5 | |
| I don't exactly understand why it has to be the way it is, but I just want it to work. Also fix a pylint complaint. | |||||
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index : riscv-tools/riscv-tests.git | |
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