| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2017-08-14 | Merge pull request #66 from riscv/debug_user_niceness | Megan Wachs | 2 | -6/+14 | |
| Debug: Usability Features | |||||
| 2017-08-14 | debug: clean up Temporary Log File messages | Megan Wachs | 1 | -2/+2 | |
| 2017-08-14 | debug: Avoid None type error | Megan Wachs | 1 | -1/+1 | |
| 2017-08-14 | debug: Revert change to print backtrace, as that is actually already printed | Megan Wachs | 1 | -2/+0 | |
| 2017-08-14 | debug: Allow OpenOCD startup timeout to be specified. Print out path to log ↵ | Megan Wachs | 2 | -5/+13 | |
| files. | |||||
| 2017-08-14 | When a test fails with exception, actually print out the reason why. | Megan Wachs | 1 | -0/+2 | |
| 2017-08-13 | Make MemTest* catch reading too many words. | Tim Newsome | 1 | -7/+6 | |
| For one of the test addresses, use the highest possible one to ensure that OpenOCD isn't secretly reading/writing more words than requested. | |||||
| 2017-08-11 | Show the OpenOCD log in all(?) failure cases. | Tim Newsome | 1 | -23/+29 | |
| 2017-08-11 | Print out name of logfile when debug test is run. | Tim Newsome | 1 | -5/+5 | |
| 2017-08-11 | When make fails to run a test, print out the log. | Tim Newsome | 2 | -2/+6 | |
| 2017-08-11 | Don't use `set pipefail` which is a bashism. | Tim Newsome | 1 | -7/+5 | |
| Instead, just give up on making the log files altogether now. Since gdbserver.py makes its own log files it's not as necessary in any case. This is yet another commit in an attempt to get the riscv-tools build to actually fail if these tests fail. | |||||
| 2017-08-11 | Don't eat errors in debug Makefile. | Tim Newsome | 1 | -0/+1 | |
| 2017-08-10 | Don't run debug tests as part of build. | Tim Newsome | 2 | -4/+3 | |
| Testing is a separate step. Also fix Issue #64 by adding src_dir to the path to the targets file. | |||||
| 2017-08-10 | Pylint target files as well. | Tim Newsome | 2 | -2/+2 | |
| This would have prevented some bugs I committed earlier. | |||||
| 2017-08-10 | Give these sim targets a chance of passing. | Tim Newsome | 3 | -5/+11 | |
| Also make sure vsim.log makes it into the generated log file. | |||||
| 2017-08-08 | Merge pull request #62 from ↵ | Palmer Dabbelt | 1 | -1/+6 | |
| richardxia/only-emit-f-instructions-when-compiled-for-f rv64[ms]i-csr: Only emit F instructions when compiled for F. | |||||
| 2017-08-07 | rv64[ms]i-csr: Only emit F instructions when compiled for F. | Richard Xia | 1 | -1/+6 | |
| 2017-08-04 | RV32 div tests should use -2^31 for min value, not -2^63 | Andrew Waterman | 3 | -9/+9 | |
| 2017-08-04 | Improve RVC test | Andrew Waterman | 3 | -9/+9 | |
| Make the page-crossing instruction non-idempotent to detect erroneously executing the first 16 bits of the instruction with garbage MSBs. | |||||
| 2017-07-31 | Fix the end of MulticoreTest. | Tim Newsome | 1 | -30/+22 | |
| Now it actually confirms that we're talking to two different cores which have different values in their registers. Previously it could have been fooled if eg. the thread command was a nop. | |||||
| 2017-07-27 | Make pylint happy. | Tim Newsome | 1 | -2/+2 | |
| 2017-07-26 | Use new OpenOCD messages to determine gdb port. | Tim Newsome | 1 | -41/+8 | |
| This is simpler and more reliable than playing around with lsof. Specifically, it works if the OpenOCD command is "strace openocd" while the previous code did not. | |||||
| 2017-07-21 | Only clean up logfiles that we know we created. | Tim Newsome | 1 | -1/+1 | |
| 2017-07-20 | Add back code to clean up triggers in entry.S | Tim Newsome | 3 | -0/+24 | |
| Then for targets that can't handle this because they don't implement hmode, add a target setting that allows that to be specified. | |||||
| 2017-07-18 | Check all PCs after reset. | Tim Newsome | 1 | -1/+7 | |
| 2017-07-12 | Print out logs in more failure cases. | Tim Newsome | 1 | -4/+10 | |
| 2017-07-06 | Merge pull request #58 from riscv/fpga_reset_halt | Tim Newsome | 1 | -0/+5 | |
| debug: Make the 'out of reset' tests apply reset | |||||
| 2017-07-06 | debug: Make the 'out of reset' tests actually apply reset | mwachs5 | 1 | -0/+5 | |
| 2017-07-03 | Add gdb_setup to target for arbitrary gdb commands | Tim Newsome | 2 | -0/+7 | |
| I'm using this for a target where misa is at an old address, to set riscv use_compressed_breakpoints off | |||||
| 2017-07-03 | Don't clear triggers during execution. | Tim Newsome | 1 | -9/+0 | |
| This shouldn't affect triggers set by the debugger, because running code can't change those. When it does affect them, it breaks Hwbp1 which sets the breakpoint before running the program. | |||||
| 2017-06-27 | Tolerate missing misa register. | Tim Newsome | 1 | -1/+7 | |
| At least in the test programs. There are other places where this causes trouble as well. | |||||
| 2017-06-27 | Merge pull request #55 from riscv/debug | Tim Newsome | 1 | -1/+1 | |
| Test gdb/OpenOCD during regular test run. | |||||
| 2017-06-27 | Merge pull request #56 from riscv/config | Tim Newsome | 26 | -284/+184 | |
| Move target definition into individual files. | |||||
| 2017-06-26 | Move target definition into individual files. | Tim Newsome | 26 | -284/+184 | |
| Instead of defining each target in targets.py, now each target gets its own .py file. This means people can easily keep their own target files around that they may not want to put into the main test source. As part of that, I removed the freedom-u500-sim target since I assume it's only used internally at SiFive. Added a few cleanups as well: * Update README examples, mostly --sim_cmd instead of --cmd. * Allow defining misa in a target, to skip running of ExamineTarget. * Rename target.target() to target.create(), which is less confusing. * Default --sim_cmd to `spike` * Got rid of `use_fpu`, instead looking at F or D in $misa. | |||||
| 2017-06-23 | Test gdb/OpenOCD during regular test run. | Tim Newsome | 1 | -1/+1 | |
| 2017-06-22 | Add basic multicore test. | Tim Newsome | 3 | -42/+128 | |
| 2017-06-20 | Smoketest multicore. | Tim Newsome | 3 | -14/+55 | |
| When connecting to gdb, select a random thread and use that for the current test. Also replace infinite_loop with something that will later allow smoketesting of more than one thread. | |||||
| 2017-06-19 | Write OpenOCD log when it crashes early. | Tim Newsome | 1 | -2/+4 | |
| 2017-06-16 | Store logs for all tests in logs/ | Tim Newsome | 1 | -30/+58 | |
| This creates a record of passing as well as failing tests, and gets rid of the log clutter that you previously ended up with in the current directory. | |||||
| 2017-06-15 | Test 64-bit addressing. | Tim Newsome | 8 | -29/+90 | |
| The spike64 target now links all test programs at 0x7fff_ffff_ffff_0000. Also a minor change to log file naming so that 'make all' works again. I'll fix this better later. | |||||
| 2017-06-09 | Add final echo to E300/U500 OpenOCD scripts | Tim Newsome | 2 | -0/+2 | |
| 2017-06-09 | Make HiFive1 testing (mostly) work again | Tim Newsome | 2 | -2/+5 | |
| Currently failing: DebugChangeString DebugFunctionCall InstantHaltTest | |||||
| 2017-06-09 | Fix using defaults for --server_cmd and --sim_cmd | Tim Newsome | 1 | -1/+1 | |
| 2017-06-09 | Default to openocd, not riscv-openocd | Tim Newsome | 1 | -1/+1 | |
| AFAICT the normal build process never builds a binary called riscv-openocd. | |||||
| 2017-06-05 | Make pylint happy. | Tim Newsome | 3 | -10/+13 | |
| If we want we can start using print(), but if so let's consistently use it instead of piecemeal. See also https://stackoverflow.com/questions/28694380/pylint-says-unnecessary-parens-after-r-keyword | |||||
| 2017-05-25 | Merge pull request #53 from richardxia/fail-if-simulator-exits-early | Palmer Dabbelt | 1 | -0/+6 | |
| Fail if simulator exits early. | |||||
| 2017-05-23 | Fail if simulator exits early. | Richard Xia | 1 | -0/+6 | |
| 2017-05-22 | minNum -> minimumNumber | Andrew Waterman | 2 | -4/+16 | |
| 2017-05-18 | Merge pull request #52 from riscv/vcs_sim_cmd | Megan Wachs | 1 | -1/+1 | |
| debug: Correct the calling for a 32-bit simulation target | |||||
| 2017-05-18 | debug: Correct the calling for a 32-bit simulation target | Megan Wachs | 1 | -1/+1 | |
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index : riscv-tools/riscv-tests.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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