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riscv-tools/riscv-tests.git
attempt-travis-fix
ceasetest2
compliance_tests
cs152-sp18-lab3
debug
debug-0.13
debug-clear-satp
debug-delete-sim
debug_auth
debug_disassemble
disable_unavailable
dma-memcpy
eos20-bringup
hw_watchpoint
interrupts
master
misc
no_progbuf
priv
privchange-dontdeleteme
python3
rekall
resume_from_trigger
riscv-tests-sail
rtos
rvt-master
smi-demo
split-isa-tests
sqrt-171
tmp
trap_entry_align
trap_entry_align-1
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2019-01-04
bump env
Andrew Waterman
1
-5
/
+5
2018-12-31
Add testing of run-test/idle cases.
Tim Newsome
7
-7
/
+17
2018-12-31
Fix MemTestBlock
Tim Newsome
1
-20
/
+41
2018-12-18
Avoid using t3 and t4 for supporting RV32E (#173)
zhonghochen
1
-5
/
+6
2018-12-03
Reduce download size a bit.
Tim Newsome
2
-6
/
+9
2018-12-03
Merge pull request #172 from riscv/downloadtest
Tim Newsome
1
-1
/
+1
2018-11-30
Use more than 1KB for download test.
Tim Newsome
1
-1
/
+1
2018-11-16
Make pylint happy.
Tim Newsome
1
-3
/
+6
2018-11-16
Test memory content on failing SC (#171)
Florian Zaruba
1
-4
/
+10
2018-11-14
Merge pull request #165 from riscv/flash
Tim Newsome
7
-18
/
+103
2018-11-14
Merge pull request #169 from riscv/eclipse_memory_read
Carsten Gosvig
4
-2
/
+59
2018-11-14
Cleanup and renamed test flag to invalid_memory_returns_zero
cgsfv
4
-6
/
+6
2018-11-13
Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fix
cgsfv
4
-2
/
+59
2018-11-12
Simpler/more idiomatic way to keep string on stack
Tim Newsome
1
-4
/
+1
2018-10-31
Add HiFive1-flash target configuration.
Tim Newsome
2
-0
/
+59
2018-10-31
Fix remaining tests to work from flash:
Tim Newsome
2
-6
/
+17
2018-10-29
Almost all tests pass with HiFive1-flash
Tim Newsome
2
-4
/
+13
2018-10-29
Tweak debug tests to run out of flash.
Tim Newsome
4
-8
/
+17
2018-10-24
Merge branch 'TriggerLoadAddressInstant'
Tim Newsome
1
-12
/
+1
2018-10-24
Re-enable TriggerStoreAddressInstant
Tim Newsome
1
-12
/
+1
2018-10-05
Make HwWatchpoint test fail on incorrect result.
hw_watchpoint
Tim Newsome
3
-7
/
+10
2018-10-03
Added tests for hw and sw watchpoints
cgsfv
3
-0
/
+88
2018-09-23
bump env
Andrew Waterman
1
-5
/
+5
2018-09-13
Assert if HiFive1 program is too large.
Tim Newsome
1
-0
/
+2
2018-09-13
Put debug test stack in data instead of text
Tim Newsome
1
-0
/
+1
2018-09-08
Merge branch 'tommythorn-master'
Andrew Waterman
6
-0
/
+42
2018-09-08
RV64 s{ll,ra,rl}w tests with non-canonical values
Tommy Thorn
6
-0
/
+42
2018-09-06
Revert "breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) ...
Andrew Waterman
1
-1
/
+1
2018-09-06
breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) (#159)
Tommy Thorn
1
-1
/
+1
2018-09-03
Merge pull request #156 from riscv/PrivChange
Tim Newsome
1
-27
/
+26
2018-08-31
Fix CustomRegisterTest.
Tim Newsome
2
-5
/
+6
2018-08-29
Add test case for `riscv expose_custom`.
Tim Newsome
12
-0
/
+55
2018-08-28
Reset address translation/perms before PrivChange
Tim Newsome
1
-27
/
+26
2018-08-27
Neuter TriggerStoreAddressInstant
Tim Newsome
1
-1
/
+13
2018-08-27
Make pylint happy.
Tim Newsome
1
-1
/
+2
2018-08-25
Temporarily disabling PrivChange test
Andrew Waterman
1
-22
/
+23
2018-08-23
Make pylint happy with change d1d2d953b5016b465.
Tim Newsome
2
-3
/
+4
2018-08-23
Get all of the log into the final log file
Tim Newsome
1
-6
/
+20
2018-08-23
Merge pull request #153 from dmitryryzhov/rtos-switch-active-thread
Tim Newsome
1
-0
/
+28
2018-08-22
Merge branch 'master' of https://github.com/riscv/riscv-tests
Tim Newsome
1
-2
/
+2
2018-08-22
Disable MulticoreRunHaltStepiTest
Tim Newsome
1
-52
/
+52
2018-08-22
Add debug test, which checks that openocd correctly switch active thread on a...
Dmitry Ryzhov
1
-0
/
+28
2018-08-21
Changing the register mstatus is read into (#152)
Srivatsa Yogendra
1
-2
/
+2
2018-08-20
Revert "Fix to solve the failing tests shamt, csr and scall (#151)"
Andrew Waterman
2
-52
/
+5
2018-08-17
Fix to solve the failing tests shamt, csr and scall (#151)
Srivatsa Yogendra
2
-5
/
+52
2018-08-17
making mtvec_handler global (#150)
Srivatsa Yogendra
1
-0
/
+1
2018-08-13
Add jump/hbreak test.
Tim Newsome
1
-0
/
+23
2018-07-09
Check that SC yields the load reservation
Andrew Waterman
1
-0
/
+9
2018-07-03
rwatch/watch on explicit address
Tim Newsome
1
-2
/
+4
2018-06-18
Add reproduce line to the end of debug test logs
Tim Newsome
1
-0
/
+2
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