diff options
Diffstat (limited to 'isa/rv64si')
| -rw-r--r-- | isa/rv64si/Makefrag | 5 | ||||
| -rw-r--r-- | isa/rv64si/illegal.S | 43 | ||||
| -rw-r--r-- | isa/rv64si/ma_addr.S | 92 | ||||
| -rw-r--r-- | isa/rv64si/ma_fetch.S | 83 | ||||
| -rw-r--r-- | isa/rv64si/sbreak.S | 43 | ||||
| -rw-r--r-- | isa/rv64si/scall.S | 43 |
6 files changed, 309 insertions, 0 deletions
diff --git a/isa/rv64si/Makefrag b/isa/rv64si/Makefrag index 87982c6..802fc55 100644 --- a/isa/rv64si/Makefrag +++ b/isa/rv64si/Makefrag @@ -4,6 +4,11 @@ rv64si_sc_tests = \ csr \ + illegal \ + ma_fetch \ + ma_addr \ + scall \ + sbreak \ timer \ dirty \ diff --git a/isa/rv64si/illegal.S b/isa/rv64si/illegal.S new file mode 100644 index 0000000..b068118 --- /dev/null +++ b/isa/rv64si/illegal.S @@ -0,0 +1,43 @@ +# See LICENSE for license details. + +#***************************************************************************** +# illegal.S +#----------------------------------------------------------------------------- +# +# Test illegal instruction trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RVTEST_CODE_BEGIN + + la t0, stvec + csrw stvec, t0 + + li TESTNUM, 2 + .word 0 + j fail + + j pass + + TEST_PASSFAIL + +stvec: + li t1, CAUSE_ILLEGAL_INSTRUCTION + csrr t0, scause + bne t0, t1, fail + csrr t0, sepc + addi t0, t0, 8 + csrw sepc, t0 + sret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64si/ma_addr.S b/isa/rv64si/ma_addr.S new file mode 100644 index 0000000..19abe96 --- /dev/null +++ b/isa/rv64si/ma_addr.S @@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ma_addr.S +#----------------------------------------------------------------------------- +# +# Test misaligned ld/st trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RVTEST_CODE_BEGIN + + la s0, stvec_load + + la t0, stvec_load + csrw stvec, t0 + +#define MISALIGNED_LDST_TEST(testnum, insn, base, offset) \ + li TESTNUM, testnum; \ + insn x0, offset(base); \ + j fail \ + + MISALIGNED_LDST_TEST(2, lh, s0, 1) + MISALIGNED_LDST_TEST(3, lhu, s0, 1) + MISALIGNED_LDST_TEST(4, lw, s0, 1) + MISALIGNED_LDST_TEST(5, lw, s0, 2) + MISALIGNED_LDST_TEST(6, lw, s0, 3) + +#ifdef __riscv64 + MISALIGNED_LDST_TEST(7, lwu, s0, 1) + MISALIGNED_LDST_TEST(8, lwu, s0, 2) + MISALIGNED_LDST_TEST(9, lwu, s0, 3) + + MISALIGNED_LDST_TEST(10, ld, s0, 1) + MISALIGNED_LDST_TEST(11, ld, s0, 2) + MISALIGNED_LDST_TEST(12, ld, s0, 3) + MISALIGNED_LDST_TEST(13, ld, s0, 4) + MISALIGNED_LDST_TEST(14, ld, s0, 5) + MISALIGNED_LDST_TEST(15, ld, s0, 6) + MISALIGNED_LDST_TEST(16, ld, s0, 7) +#endif + + la t0, stvec_store + csrw stvec, t0 + + MISALIGNED_LDST_TEST(22, sh, s0, 1) + MISALIGNED_LDST_TEST(23, sw, s0, 1) + MISALIGNED_LDST_TEST(24, sw, s0, 2) + MISALIGNED_LDST_TEST(25, sw, s0, 3) + +#ifdef __riscv64 + MISALIGNED_LDST_TEST(26, sd, s0, 1) + MISALIGNED_LDST_TEST(27, sd, s0, 2) + MISALIGNED_LDST_TEST(28, sd, s0, 3) + MISALIGNED_LDST_TEST(29, sd, s0, 4) + MISALIGNED_LDST_TEST(30, sd, s0, 5) + MISALIGNED_LDST_TEST(31, sd, s0, 6) + MISALIGNED_LDST_TEST(32, sd, s0, 7) +#endif + + TEST_PASSFAIL + + .align 3 +stvec_load: + li t1, CAUSE_MISALIGNED_LOAD + csrr t0, scause + bne t0, t1, fail + csrr t0, sepc + addi t0, t0, 8 + csrw sepc, t0 + sret + +stvec_store: + li t1, CAUSE_MISALIGNED_STORE + csrr t0, scause + bne t0, t1, fail + csrr t0, sepc + addi t0, t0, 8 + csrw sepc, t0 + sret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S new file mode 100644 index 0000000..ae8377d --- /dev/null +++ b/isa/rv64si/ma_fetch.S @@ -0,0 +1,83 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ma_fetch.S +#----------------------------------------------------------------------------- +# +# Test misaligned fetch trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RVTEST_CODE_BEGIN + + la t0, stvec + csrw stvec, t0 + +#ifndef __rvc + li TESTNUM, 2 + li t1, 0 + la t0, 1f + jalr t1, t0, 2 +1: + j fail +#endif + + // This test should pass, since JALR ignores the target LSB + li TESTNUM, 3 + la t0, 1f + jalr t1, t0, 1 +1: + j 1f + j fail +1: + +#ifndef __rvc + li TESTNUM, 4 + li t1, 0 + la t0, 3f + jr t0, 3 +3: + j fail +#endif + + j pass + + TEST_PASSFAIL + +stvec: + # tests 2 and 4 should trap + li a0, 2 + beq TESTNUM, a0, 1f + li a0, 4 + beq TESTNUM, a0, 1f + j fail +1: + + # verify that return address was not written + bnez t1, fail + + # verify trap cause + li a1, CAUSE_MISALIGNED_FETCH + csrr a0, scause + bne a0, a1, fail + + # verify that epc == &jalr (== t0 - 4) + csrr a1, sepc + addi t0, t0, -4 + bne t0, a1, fail + + addi a1, a1, 8 + csrw sepc, a1 + sret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64si/sbreak.S b/isa/rv64si/sbreak.S new file mode 100644 index 0000000..dbdf7ae --- /dev/null +++ b/isa/rv64si/sbreak.S @@ -0,0 +1,43 @@ +# See LICENSE for license details. + +#***************************************************************************** +# scall.S +#----------------------------------------------------------------------------- +# +# Test syscall trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RVTEST_CODE_BEGIN + + la t0, stvec + csrw stvec, t0 + + li TESTNUM, 2 + sbreak + j fail + + j pass + + TEST_PASSFAIL + +stvec: + li t1, CAUSE_BREAKPOINT + csrr t0, scause + bne t0, t1, fail + csrr t0, sepc + addi t0, t0, 8 + csrw sepc, t0 + sret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S new file mode 100644 index 0000000..aa543e9 --- /dev/null +++ b/isa/rv64si/scall.S @@ -0,0 +1,43 @@ +# See LICENSE for license details. + +#***************************************************************************** +# scall.S +#----------------------------------------------------------------------------- +# +# Test syscall trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RVTEST_CODE_BEGIN + + la t0, stvec + csrw stvec, t0 + + li TESTNUM, 2 + scall + j fail + + j pass + + TEST_PASSFAIL + +stvec: + li t1, CAUSE_ECALL + csrr t0, scause + bne t0, t1, fail + csrr t0, sepc + addi t0, t0, 8 + csrw sepc, t0 + sret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END |