diff options
Diffstat (limited to 'isa/rv32uzbb')
| -rw-r--r-- | isa/rv32uzbb/Makefrag | 26 | ||||
| -rw-r--r-- | isa/rv32uzbb/andn.S | 7 | ||||
| -rw-r--r-- | isa/rv32uzbb/clz.S | 76 | ||||
| -rw-r--r-- | isa/rv32uzbb/cpop.S | 75 | ||||
| -rw-r--r-- | isa/rv32uzbb/ctz.S | 75 | ||||
| -rw-r--r-- | isa/rv32uzbb/max.S | 7 | ||||
| -rw-r--r-- | isa/rv32uzbb/maxu.S | 7 | ||||
| -rw-r--r-- | isa/rv32uzbb/min.S | 7 | ||||
| -rw-r--r-- | isa/rv32uzbb/minu.S | 7 | ||||
| -rw-r--r-- | isa/rv32uzbb/orc_b.S | 75 | ||||
| -rw-r--r-- | isa/rv32uzbb/orn.S | 7 | ||||
| -rw-r--r-- | isa/rv32uzbb/rev8.S | 75 | ||||
| -rw-r--r-- | isa/rv32uzbb/rol.S | 97 | ||||
| -rw-r--r-- | isa/rv32uzbb/ror.S | 91 | ||||
| -rw-r--r-- | isa/rv32uzbb/rori.S | 68 | ||||
| -rw-r--r-- | isa/rv32uzbb/sext_b.S | 7 | ||||
| -rw-r--r-- | isa/rv32uzbb/sext_h.S | 7 | ||||
| -rw-r--r-- | isa/rv32uzbb/xnor.S | 7 | ||||
| -rw-r--r-- | isa/rv32uzbb/zext_h.S | 7 |
19 files changed, 728 insertions, 0 deletions
diff --git a/isa/rv32uzbb/Makefrag b/isa/rv32uzbb/Makefrag new file mode 100644 index 0000000..752f8d0 --- /dev/null +++ b/isa/rv32uzbb/Makefrag @@ -0,0 +1,26 @@ +#======================================================================= +# Makefrag for rv32uzbb tests +#----------------------------------------------------------------------- + +rv32uzbb_sc_tests = \ + andn \ + clz \ + cpop \ + ctz \ + max maxu \ + min minu \ + orc_b \ + orn \ + rev8 \ + rol \ + ror \ + rori \ + sext_b sext_h \ + xnor \ + zext_h \ + +rv32uzbb_p_tests = $(addprefix rv32uzbb-p-, $(rv32uzbb_sc_tests)) +rv32uzbb_v_tests = $(addprefix rv32uzbb-v-, $(rv32uzbb_sc_tests)) +rv32uzbb_ps_tests = $(addprefix rv32uzbb-ps-, $(rv32uzbb_sc_tests)) + +spike_tests += $(rv32uzbb_p_tests) $(rv32uzbb_v_tests) diff --git a/isa/rv32uzbb/andn.S b/isa/rv32uzbb/andn.S new file mode 100644 index 0000000..f54aa1a --- /dev/null +++ b/isa/rv32uzbb/andn.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/andn.S" diff --git a/isa/rv32uzbb/clz.S b/isa/rv32uzbb/clz.S new file mode 100644 index 0000000..4b349ad --- /dev/null +++ b/isa/rv32uzbb/clz.S @@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clz.S +#----------------------------------------------------------------------------- +# +# Test clz instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, clz, 32, 0x00000000); + TEST_R_OP( 3, clz, 31, 0x00000001); + TEST_R_OP( 4, clz, 30, 0x00000003); + + TEST_R_OP( 5, clz, 0, 0xffff8000 ); + TEST_R_OP( 6, clz, 8, 0x00800000 ); + TEST_R_OP( 7, clz, 0, 0xffff8000 ); + + TEST_R_OP( 8, clz, 17, 0x00007fff); + TEST_R_OP( 9, clz, 1, 0x7fffffff); + TEST_R_OP( 10, clz, 13, 0x0007ffff ); + + TEST_R_OP( 11, clz, 0, 0x80000000); + TEST_R_OP( 12, clz, 3, 0x121f5000); + + TEST_R_OP( 13, clz, 5, 0x04000000); + TEST_R_OP( 14, clz, 28, 0x0000000e); + TEST_R_OP( 15, clz, 2, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, clz, 28, 13); + TEST_R_SRC1_EQ_DEST( 17, clz, 28, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, clz, 28, 13); + TEST_R_DEST_BYPASS( 29, 1, clz, 27, 19); + TEST_R_DEST_BYPASS( 20, 2, clz, 26, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + + TEST_R_OP( 21, clz, 5, 0x070f8000 ); + TEST_R_OP( 22, clz, 4, 0x08008000 ); + TEST_R_OP( 23, clz, 3, 0x18008000 ); + + TEST_R_OP( 24, clz, 17, 0x00007fff); + TEST_R_OP( 25, clz, 1, 0x7fffffff); + TEST_R_OP( 26, clz, 13, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/cpop.S b/isa/rv32uzbb/cpop.S new file mode 100644 index 0000000..4d97758 --- /dev/null +++ b/isa/rv32uzbb/cpop.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# cpop.S +#----------------------------------------------------------------------------- +# +# Test cpop instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, cpop, 0, 0x00000000); + TEST_R_OP( 3, cpop, 1, 0x00000001); + TEST_R_OP( 4, cpop, 2, 0x00000003); + + TEST_R_OP( 5, cpop, 17, 0xffff8000 ); + TEST_R_OP( 6, cpop, 1, 0x00800000 ); + TEST_R_OP( 7, cpop, 18, 0xffff6000 ); + + TEST_R_OP( 8, cpop, 15, 0x00007fff); + TEST_R_OP( 9, cpop, 31, 0x7fffffff); + TEST_R_OP( 10, cpop, 19, 0x0007ffff ); + + TEST_R_OP( 11, cpop, 1, 0x80000000); + TEST_R_OP( 12, cpop, 9, 0x121f5000); + + TEST_R_OP( 13, cpop, 0, 0x00000000); + TEST_R_OP( 14, cpop, 3, 0x0000000e); + TEST_R_OP( 15, cpop, 7, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, cpop, 3, 13); + TEST_R_SRC1_EQ_DEST( 17, cpop, 3, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, cpop, 3, 13); + TEST_R_DEST_BYPASS( 29, 1, cpop, 3, 19); + TEST_R_DEST_BYPASS( 20, 2, cpop, 2, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, cpop, 8, 0x007f8000 ); + TEST_R_OP( 22, cpop, 2, 0x00808000 ); + TEST_R_OP( 23, cpop, 3, 0x01808000 ); + + TEST_R_OP( 24, cpop, 17, 0x30007fff); + TEST_R_OP( 25, cpop, 30, 0x77ffffff); + TEST_R_OP( 26, cpop, 19, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/ctz.S b/isa/rv32uzbb/ctz.S new file mode 100644 index 0000000..58bf2f1 --- /dev/null +++ b/isa/rv32uzbb/ctz.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ctz.S +#----------------------------------------------------------------------------- +# +# Test ctz instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, ctz, 32, 0x00000000); + TEST_R_OP( 3, ctz, 0, 0x00000001); + TEST_R_OP( 4, ctz, 0, 0x00000003); + + TEST_R_OP( 5, ctz, 15, 0xffff8000 ); + TEST_R_OP( 6, ctz, 23, 0x00800000 ); + TEST_R_OP( 7, ctz, 15, 0xffff8000 ); + + TEST_R_OP( 8, ctz, 0, 0x00007fff); + TEST_R_OP( 9, ctz, 0, 0x7fffffff); + TEST_R_OP( 10, ctz, 0, 0x0007ffff ); + + TEST_R_OP( 11, ctz, 31, 0x80000000); + TEST_R_OP( 12, ctz, 12, 0x121f5000); + + TEST_R_OP( 13, ctz, 30, 0xc0000000); + TEST_R_OP( 14, ctz, 1, 0x0000000e); + TEST_R_OP( 15, ctz, 0, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, ctz, 0, 13); + TEST_R_SRC1_EQ_DEST( 17, ctz, 0, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, ctz, 0, 13); + TEST_R_DEST_BYPASS( 29, 1, ctz, 0, 19); + TEST_R_DEST_BYPASS( 20, 2, ctz, 1, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, ctz, 15, 0x007f8000 ); + TEST_R_OP( 22, ctz, 15, 0x00808000 ); + TEST_R_OP( 23, ctz, 12, 0x01809000 ); + + TEST_R_OP( 24, ctz, 0, 0x00007fff); + TEST_R_OP( 25, ctz, 0, 0x7fffffff); + TEST_R_OP( 26, ctz, 0, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/max.S b/isa/rv32uzbb/max.S new file mode 100644 index 0000000..ecd713c --- /dev/null +++ b/isa/rv32uzbb/max.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/max.S" diff --git a/isa/rv32uzbb/maxu.S b/isa/rv32uzbb/maxu.S new file mode 100644 index 0000000..27cfc29 --- /dev/null +++ b/isa/rv32uzbb/maxu.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/maxu.S" diff --git a/isa/rv32uzbb/min.S b/isa/rv32uzbb/min.S new file mode 100644 index 0000000..c24a514 --- /dev/null +++ b/isa/rv32uzbb/min.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/min.S" diff --git a/isa/rv32uzbb/minu.S b/isa/rv32uzbb/minu.S new file mode 100644 index 0000000..4b2549d --- /dev/null +++ b/isa/rv32uzbb/minu.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/minu.S" diff --git a/isa/rv32uzbb/orc_b.S b/isa/rv32uzbb/orc_b.S new file mode 100644 index 0000000..7fb8441 --- /dev/null +++ b/isa/rv32uzbb/orc_b.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# orc.b.S +#----------------------------------------------------------------------------- +# +# Test orc.b instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, orc.b, 0x00000000, 0x00000000); + TEST_R_OP( 3, orc.b, 0x000000ff, 0x00000001); + TEST_R_OP( 4, orc.b, 0x000000ff, 0x00000003); + + TEST_R_OP( 5, orc.b, 0xffffff00, 0xffff8000 ); + TEST_R_OP( 6, orc.b, 0x00ff0000, 0x00800000 ); + TEST_R_OP( 7, orc.b, 0xffffff00, 0xffff8000 ); + + TEST_R_OP( 8, orc.b, 0x0000ffff, 0x00007fff); + TEST_R_OP( 9, orc.b, 0xffffffff, 0x7fffffff); + TEST_R_OP( 10, orc.b, 0x00ffffff, 0x0007ffff ); + + TEST_R_OP( 11, orc.b, 0xff000000, 0x80000000); + TEST_R_OP( 12, orc.b, 0xffffff00, 0x121f5000); + + TEST_R_OP( 13, orc.b, 0x00000000, 0x00000000); + TEST_R_OP( 14, orc.b, 0x000000ff, 0x0000000e); + TEST_R_OP( 15, orc.b, 0xffffffff, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, orc.b, 0xff, 13); + TEST_R_SRC1_EQ_DEST( 17, orc.b, 0xff, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, orc.b, 0xff, 13); + TEST_R_DEST_BYPASS( 29, 1, orc.b, 0xff, 19); + TEST_R_DEST_BYPASS( 20, 2, orc.b, 0xff, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, orc.b, 0x00ffff00, 0x007f8000 ); + TEST_R_OP( 22, orc.b, 0x00ffff00, 0x00808000 ); + TEST_R_OP( 23, orc.b, 0xffffff00, 0x01808000 ); + + TEST_R_OP( 24, orc.b, 0x0000ffff, 0x00007fff); + TEST_R_OP( 25, orc.b, 0xffffffff, 0x7fffffff); + TEST_R_OP( 26, orc.b, 0x00ffffff, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/orn.S b/isa/rv32uzbb/orn.S new file mode 100644 index 0000000..cdfafcc --- /dev/null +++ b/isa/rv32uzbb/orn.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/orn.S" diff --git a/isa/rv32uzbb/rev8.S b/isa/rv32uzbb/rev8.S new file mode 100644 index 0000000..2828f27 --- /dev/null +++ b/isa/rv32uzbb/rev8.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rev8.S +#----------------------------------------------------------------------------- +# +# Test rev8 instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, rev8, 0x00000000, 0x00000000); + TEST_R_OP( 3, rev8, 0x01000000, 0x00000001); + TEST_R_OP( 4, rev8, 0x03000000, 0x00000003); + + TEST_R_OP( 5, rev8, 0x0080ffff, 0xffff8000 ); + TEST_R_OP( 6, rev8, 0x00008000, 0x00800000 ); + TEST_R_OP( 7, rev8, 0x0080ffff, 0xffff8000 ); + + TEST_R_OP( 8, rev8, 0xff7f0000, 0x00007fff); + TEST_R_OP( 9, rev8, 0xffffff7f, 0x7fffffff); + TEST_R_OP( 10, rev8, 0xffff0700, 0x0007ffff ); + + TEST_R_OP( 11, rev8, 0x00000080, 0x80000000); + TEST_R_OP( 12, rev8, 0x00501f12, 0x121f5000); + + TEST_R_OP( 13, rev8, 0x00000000, 0x00000000); + TEST_R_OP( 14, rev8, 0x0e000000, 0x0000000e); + TEST_R_OP( 15, rev8, 0x41134020, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, rev8, 0x0d000000, 13); + TEST_R_SRC1_EQ_DEST( 17, rev8, 0x0b000000, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, rev8, 0x0d000000, 13); + TEST_R_DEST_BYPASS( 29, 1, rev8, 0x13000000, 19); + TEST_R_DEST_BYPASS( 20, 2, rev8, 0x22000000, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, rev8, 0x00807f00, 0x007f8000 ); + TEST_R_OP( 22, rev8, 0x00808000, 0x00808000 ); + TEST_R_OP( 23, rev8, 0x00808001, 0x01808000 ); + + TEST_R_OP( 24, rev8, 0xff7f0000, 0x00007fff); + TEST_R_OP( 25, rev8, 0xffffff7f, 0x7fffffff); + TEST_R_OP( 26, rev8, 0xffff0700, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/rol.S b/isa/rv32uzbb/rol.S new file mode 100644 index 0000000..a7c04fe --- /dev/null +++ b/isa/rv32uzbb/rol.S @@ -0,0 +1,97 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rol.S +#----------------------------------------------------------------------------- +# +# Test rol instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rol, 0x00000001, 0x00000001, 0 ); + TEST_RR_OP( 3, rol, 0x00000002, 0x00000001, 1 ); + TEST_RR_OP( 4, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_OP( 5, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_OP( 6, rol, 0x80000000, 0x00000001, 31 ); + + TEST_RR_OP( 7, rol, 0xffffffff, 0xffffffff, 0 ); + TEST_RR_OP( 8, rol, 0xffffffff, 0xffffffff, 1 ); + TEST_RR_OP( 9, rol, 0xffffffff, 0xffffffff, 7 ); + TEST_RR_OP( 10, rol, 0xffffffff, 0xffffffff, 14 ); + TEST_RR_OP( 11, rol, 0xffffffff, 0xffffffff, 31 ); + + TEST_RR_OP( 12, rol, 0x21212121, 0x21212121, 0 ); + TEST_RR_OP( 13, rol, 0x42424242, 0x21212121, 1 ); + TEST_RR_OP( 14, rol, 0x90909090, 0x21212121, 7 ); + TEST_RR_OP( 15, rol, 0x48484848, 0x21212121, 14 ); + TEST_RR_OP( 16, rol, 0x90909090, 0x21212121, 31 ); + + # Verify that rotates only use bottom five bits + + TEST_RR_OP( 17, rol, 0x21212121, 0x21212121, 0xffffffe0 ); + TEST_RR_OP( 18, rol, 0x42424242, 0x21212121, 0xffffffe1 ); + TEST_RR_OP( 19, rol, 0x90909090, 0x21212121, 0xffffffe7 ); + TEST_RR_OP( 20, rol, 0x48484848, 0x21212121, 0xffffffee ); + TEST_RR_OP( 21, rol, 0x90909090, 0x21212121, 0xffffffff ); + + # Verify that rotates ignore top 32 (using true 64-bit values) + + TEST_RR_OP( 44, rol, 0x12345678, 0x12345678, 0 ); + TEST_RR_OP( 45, rol, 0x23456781, 0x12345678, 4 ); + TEST_RR_OP( 46, rol, 0x92345678, 0x92345678, 0 ); + TEST_RR_OP( 47, rol, 0x93456789, 0x99345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, rol, 24, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, rol, 0x80000000, 0x00000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, rol, 0x80000000, 0x00000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, rol, 0x80000000, 0x00000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, rol, 0x80000000, 0x00000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, rol, 0x80000000, 0x00000001, 31 ); + + TEST_RR_ZEROSRC1( 40, rol, 0, 15 ); + TEST_RR_ZEROSRC2( 41, rol, 32, 32 ); + TEST_RR_ZEROSRC12( 42, rol, 0 ); + TEST_RR_ZERODEST( 43, rol, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/ror.S b/isa/rv32uzbb/ror.S new file mode 100644 index 0000000..5b57740 --- /dev/null +++ b/isa/rv32uzbb/ror.S @@ -0,0 +1,91 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ror.S +#----------------------------------------------------------------------------- +# +# Test ror instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, ror, 0x00000001, 0x00000001, 0 ); + TEST_RR_OP( 3, ror, 0x80000000, 0x00000001, 1 ); + TEST_RR_OP( 4, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_OP( 5, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_OP( 6, ror, 0x00000002, 0x00000001, 31 ); + + TEST_RR_OP( 7, ror, 0xffffffff, 0xffffffff, 0 ); + TEST_RR_OP( 8, ror, 0xffffffff, 0xffffffff, 1 ); + TEST_RR_OP( 9, ror, 0xffffffff, 0xffffffff, 7 ); + TEST_RR_OP( 10, ror, 0xffffffff, 0xffffffff, 14 ); + TEST_RR_OP( 11, ror, 0xffffffff, 0xffffffff, 31 ); + + TEST_RR_OP( 12, ror, 0x21212121, 0x21212121, 0 ); + TEST_RR_OP( 13, ror, 0x90909090, 0x21212121, 1 ); + TEST_RR_OP( 14, ror, 0x42424242, 0x21212121, 7 ); + TEST_RR_OP( 15, ror, 0x84848484, 0x21212121, 14 ); + TEST_RR_OP( 16, ror, 0x42424242, 0x21212121, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, ror, 0x21212121, 0x21212121, 0xffffffc0 ); + TEST_RR_OP( 18, ror, 0x90909090, 0x21212121, 0xffffffc1 ); + TEST_RR_OP( 19, ror, 0x42424242, 0x21212121, 0xffffffc7 ); + TEST_RR_OP( 20, ror, 0x84848484, 0x21212121, 0xffffffce ); + + TEST_RR_OP( 21, ror, 0x42424242, 0x21212121, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, ror, 0x60000000, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, ror, 0x00000002, 0x00000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, ror, 0x00000002, 0x00000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, ror, 0x00000002, 0x00000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, ror, 0x00000002, 0x00000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, ror, 0x00000002, 0x00000001, 31 ); + + TEST_RR_ZEROSRC1( 40, ror, 0, 15 ); + TEST_RR_ZEROSRC2( 41, ror, 32, 32 ); + TEST_RR_ZEROSRC12( 42, ror, 0 ); + TEST_RR_ZERODEST( 43, ror, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/rori.S b/isa/rv32uzbb/rori.S new file mode 100644 index 0000000..c98ed85 --- /dev/null +++ b/isa/rv32uzbb/rori.S @@ -0,0 +1,68 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rori.S +#----------------------------------------------------------------------------- +# +# Test rori instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, rori, 0x00000001, 0x00000001, 0 ); + TEST_IMM_OP( 3, rori, 0x80000000, 0x00000001, 1 ); + TEST_IMM_OP( 4, rori, 0x02000000, 0x00000001, 7 ); + TEST_IMM_OP( 5, rori, 0x00040000, 0x00000001, 14 ); + TEST_IMM_OP( 6, rori, 0x00000002, 0x00000001, 31 ); + + TEST_IMM_OP( 7, rori, 0xffffffff, 0xffffffff, 0 ); + TEST_IMM_OP( 8, rori, 0xffffffff, 0xffffffff, 1 ); + TEST_IMM_OP( 9, rori, 0xffffffff, 0xffffffff, 7 ); + TEST_IMM_OP( 10, rori, 0xffffffff, 0xffffffff, 14 ); + TEST_IMM_OP( 11, rori, 0xffffffff, 0xffffffff, 31 ); + + TEST_IMM_OP( 12, rori, 0x21212121, 0x21212121, 0 ); + TEST_IMM_OP( 13, rori, 0x90909090, 0x21212121, 1 ); + TEST_IMM_OP( 14, rori, 0x42424242, 0x21212121, 7 ); + TEST_IMM_OP( 15, rori, 0x84848484, 0x21212121, 14 ); + TEST_IMM_OP( 16, rori, 0x42424242, 0x21212121, 31 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 20, rori, 0x02000000, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 21, 0, rori, 0x02000000, 0x00000001, 7 ); + TEST_IMM_DEST_BYPASS( 22, 1, rori, 0x00040000, 0x00000001, 14 ); + TEST_IMM_DEST_BYPASS( 23, 2, rori, 0x00000002, 0x00000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 24, 0, rori, 0x02000000, 0x00000001, 7 ); + TEST_IMM_SRC1_BYPASS( 25, 1, rori, 0x00040000, 0x00000001, 14 ); + TEST_IMM_SRC1_BYPASS( 26, 2, rori, 0x00000002, 0x00000001, 31 ); + + TEST_IMM_ZEROSRC1( 27, rori, 0, 31 ); + TEST_IMM_ZERODEST( 28, rori, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/sext_b.S b/isa/rv32uzbb/sext_b.S new file mode 100644 index 0000000..f73e107 --- /dev/null +++ b/isa/rv32uzbb/sext_b.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/sext_b.S" diff --git a/isa/rv32uzbb/sext_h.S b/isa/rv32uzbb/sext_h.S new file mode 100644 index 0000000..d4b4206 --- /dev/null +++ b/isa/rv32uzbb/sext_h.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/sext_h.S" diff --git a/isa/rv32uzbb/xnor.S b/isa/rv32uzbb/xnor.S new file mode 100644 index 0000000..c5e453a --- /dev/null +++ b/isa/rv32uzbb/xnor.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/xnor.S" diff --git a/isa/rv32uzbb/zext_h.S b/isa/rv32uzbb/zext_h.S new file mode 100644 index 0000000..d339ccc --- /dev/null +++ b/isa/rv32uzbb/zext_h.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/zext_h.S" |