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-rw-r--r--debug/targets/SiFive/HiFive1.cfg4
1 files changed, 4 insertions, 0 deletions
diff --git a/debug/targets/SiFive/HiFive1.cfg b/debug/targets/SiFive/HiFive1.cfg
index 5bde59b..8f21b47 100644
--- a/debug/targets/SiFive/HiFive1.cfg
+++ b/debug/targets/SiFive/HiFive1.cfg
@@ -17,6 +17,10 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1
#-rtos riscv
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+riscv expose_csrs 2288
+
flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
init
#reset