diff options
Diffstat (limited to 'debug/targets/RISC-V/spike-rtos.cfg')
| -rw-r--r-- | debug/targets/RISC-V/spike-rtos.cfg | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/debug/targets/RISC-V/spike-rtos.cfg b/debug/targets/RISC-V/spike-rtos.cfg index 159a70f..d8bd27e 100644 --- a/debug/targets/RISC-V/spike-rtos.cfg +++ b/debug/targets/RISC-V/spike-rtos.cfg @@ -12,6 +12,7 @@ set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv gdb_report_data_abort enable +gdb_report_register_access_error enable # Expose an unimplemented CSR so we can test non-existent register access # behavior. |