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Diffstat (limited to 'debug/targets/RISC-V/spike-2.cfg')
| -rw-r--r-- | debug/targets/RISC-V/spike-2.cfg | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg index 114d5b8..ef8bab1 100644 --- a/debug/targets/RISC-V/spike-2.cfg +++ b/debug/targets/RISC-V/spike-2.cfg @@ -14,6 +14,7 @@ target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0 target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1 gdb_report_data_abort enable +gdb_report_register_access_error enable # Expose an unimplemented CSR so we can test non-existent register access # behavior. |