diff options
| -rwxr-xr-x | debug/gdbserver.py | 67 | ||||
| -rw-r--r-- | debug/programs/init.h | 6 | ||||
| -rw-r--r-- | debug/programs/run_halt_timing.S | 6 | ||||
| -rw-r--r-- | debug/targets.py | 6 |
4 files changed, 78 insertions, 7 deletions
diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 4b2291c..86359c8 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -913,7 +913,7 @@ class RepeatReadTest(DebugTest): def test(self): self.gdb.b("main:start") self.gdb.c() - mtime_addr = 0x02000000 + 0xbff8 + mtime_addr = self.target.clint_addr + 0xbff8 count = 1024 output = self.gdb.command( f"monitor riscv repeat_read {count} 0x{mtime_addr:x} 4") @@ -1049,8 +1049,8 @@ class InterruptTest(GdbSingleHartTest): def postMortem(self): GdbSingleHartTest.postMortem(self) - self.gdb.p("*((long long*) 0x200bff8)") - self.gdb.p("*((long long*) 0x2004000)") + self.gdb.p(f"*((long long*) 0x{self.target.clint_addr + 0xbff8:x})") + self.gdb.p(f"*((long long*) 0x{self.target.clint_addr + 0x4000:x})") self.gdb.p("interrupt_count") self.gdb.p("local") @@ -1864,6 +1864,7 @@ class UnavailableMultiTest(GdbTest): self.gdb.p("$pc=_start") self.exit() + class CeaseStepiTest(ProgramTest): """Test that we work correctly when the hart we're debugging ceases to respond.""" @@ -1951,6 +1952,66 @@ class UnavailableCycleTest(ProgramTest): self.gdb.interrupt() self.gdb.p("$pc") +class UnavailableHaltedTest(ProgramTest): + """Test behavior when the current hart becomes unavailable while halted.""" + def early_applicable(self): + return self.target.support_unavailable_control + + def test_resume(self, c_expect=None): + # Confirm things don't completely fall apart on `c` + self.gdb.c(wait=False) + if c_expect: + self.gdb.expect(c_expect) + else: + time.sleep(1) + + # Now send a DMI command through OpenOCD to make the hart available + # again. + self.server.set_available(self.target.harts) + + # The hart will show up as halted. That's just how spike behaves when we + # make a hart unavailable while it's halted. + + self.gdb.expect("became available") + self.gdb.p("$minstret") + + def test(self): + self.gdb.b("main") + output = self.gdb.c() + assertIn("Breakpoint", output) + assertIn("main", output) + + self.server.set_available( + [h for h in self.target.harts if h != self.hart]) + self.gdb.command(f"# disabled hart {self.hart.id}") + # gdb won't show that the hart became unavailable, because it thinks + # nothing can changed on a halted Linux thread. + try: + # We can't try this with something reasonable like $pc, because gdb + # has cached it, and it assumes the target can't change while it's + # halted. + self.gdb.p("$minstret") + assert False, ("Registers shouldn't be accessible when the hart is " + "unavailable.") + except testlib.CouldNotFetch: + pass + + # There's a breakpoint set, so gdb will single step. You can't single + # step an unavailable target, so gdb should get a message to that + # effect. + self.test_resume(c_expect="unavailable") + + # Delete breakpoints + self.gdb.command("delete") + self.server.set_available( + [h for h in self.target.harts if h != self.hart]) + + # Resume again. With breakpoints cleared, gdb will send vCont;c instead + # of step. There should be no error this time, since there is no + # observable difference between an unavailable thread and a running + # thread. + self.test_resume() + class FreeRtosTest(GdbTest): def early_applicable(self): return self.target.freertos_binary diff --git a/debug/programs/init.h b/debug/programs/init.h index 06d5384..e79681d 100644 --- a/debug/programs/init.h +++ b/debug/programs/init.h @@ -1,8 +1,10 @@ #ifndef INIT_H #define INIT_H -#define MTIME (*(volatile long long *)(0x02000000 + 0xbff8)) -#define MTIMECMP ((volatile long long *)(0x02000000 + 0x4000)) +#ifdef CLINT +#define MTIME (*(volatile long long *)(CLINT + 0xbff8)) +#define MTIMECMP ((volatile long long *)(CLINT + 0x4000)) +#endif typedef void* (*trap_handler_t)(unsigned hartid, unsigned mcause, void *mepc, void *sp); diff --git a/debug/programs/run_halt_timing.S b/debug/programs/run_halt_timing.S index ce4000a..dc5d58b 100644 --- a/debug/programs/run_halt_timing.S +++ b/debug/programs/run_halt_timing.S @@ -8,10 +8,14 @@ # define REGBYTES 4 #endif +#ifdef CLINT +#define MTIME_ADDR CLINT + 0xbff8 +#endif + .global main main: li s0, 0 - li s1, 0x0200bff8 + li s1, MTIME_ADDR loop: addi s0, s0, 1 LREG s2, 0(s1) diff --git a/debug/targets.py b/debug/targets.py index c1633e9..189d79b 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -96,9 +96,12 @@ class Target: # before starting the test. gdb_setup = [] - # Supports mtime at 0x2004000 + # Supports mtime default at clint_addr + 0x4000 supports_clint_mtime = True + # CLINT register address, set to the default value of spike. + clint_addr = 0x02000000 + # Implements custom debug registers like spike does. It seems unlikely any # hardware will every do that. implements_custom_test = False @@ -192,6 +195,7 @@ class Target: Target.temporary_files.append(self.temporary_binary) args = list(sources) + [ + f"-DCLINT={self.clint_addr}", "programs/entry.S", "programs/init.c", f"-DNHARTS={len(self.harts)}", "-I", "../env", |